LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 176

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that
will be used next by hardware and software. Both register act as counters starting at 0 and
wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex
contains the index of the next descriptor that is going to be filled by the software driver.
The TxConsumeIndex contains the index of the next descriptor going to be transmitted by
the hardware. When TxProduceIndex == TxConsumeIndex, the transmit buffer is empty.
When TxProduceIndex == TxConsumeIndex -1 (taking wraparound into account), the
transmit buffer is full and the software driver cannot add new descriptors until the
hardware has transmitted one or more frames to free up descriptors.
Each transmit descriptor takes two word locations (8 bytes) in memory. Likewise each
status field takes one word (4 bytes) in memory. Each transmit descriptor consists of a
pointer to the data buffer containing transmit data (Packet) and a control word (Control).
The Packet field has a zero address offset, whereas the control field has a 4 byte address
offset, see
Table 180. Transmit descriptor fields
The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the
base address of the data buffer. The definition of the control word bits is listed in
Table
Table 181. Transmit descriptor control word
Table 182
Table 182. Transmit status fields
Symbol
Packet
Control
Bit
10:0
25:11 -
26
27
28
29
30
31
Symbol
StatusInfo
181.
Symbol
Size
Override
Huge
Pad
CRC
Last
Interrupt
shows the one field transmit status.
Address offset
0x0
0x4
Table
All information provided in this document is subject to legal disclaimers.
Address
offset
0x0
180.
Description
Size in bytes of the data buffer. This is the size of the frame or fragment as it
needs to be fetched by the DMA manager. In most cases it will be equal to the
byte size of the data buffer pointed to by the Packet field of the descriptor. Size
is -1 encoded e.g. a buffer of 8 bytes is encoded as the Size value 7.
Unused
Per frame override. If true, bits 30:27 will override the defaults from the MAC
internal registers. If false, bits 30:27 will be ignored and the default values
from the MAC will be used.
If true, enables huge frame, allowing unlimited frame sizes. When false,
prevents transmission of more than the maximum frame length (MAXF[15:0]).
If true, pad short frames to 64 bytes.
If true, append a hardware CRC to the frame.
If true, indicates that this is the descriptor for the last fragment in the transmit
frame. If false, the fragment from the next descriptor should be appended.
If true, a TxDone interrupt will be generated when the data in this frame or
frame fragment has been sent and the associated status information has been
committed to memory.
Rev. 2 — 19 August 2010
Bytes
4
4
Bytes
4
Description
Base address of the data buffer containing transmit data.
Control information, see
Description
Transmit status return flags, see
Chapter 10: LPC17xx Ethernet
Table
181.
UM10360
© NXP B.V. 2010. All rights reserved.
Table
183.
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