LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 175
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
Fig 20. Transmit descriptor memory layout
TxDescriptorNumber
10.15.2 Transmit descriptors and statuses
TxDescriptor
1
2
3
4
5
[1]
For multi-fragment frames, the value of the AlignmentError, RangeError, LengthError,
SymbolError and CRCError bits in all but the last fragment in the frame will be 0; likewise
the value of the FailFilter, Multicast, Broadcast, VLAN and ControlFrame bits is undefined.
The status of the last fragment in the frame will copy the value for these bits from the
MAC. All fragment statuses will have valid LastFrag, RxSize, Error, Overrun and
NoDescriptor bits.
Figure 20
Transmit descriptors are stored in an array in memory. The lowest address of the transmit
descriptor array is stored in the TxDescriptor register, and must be aligned on a 4 byte
address boundary. The number of descriptors in the array is stored in the
TxDescriptorNumber register using a minus one encoding style i.e. if the array has 8
elements the register value should be 7. Parallel to the descriptors there is an array of
statuses. For each element of the descriptor array there is an associated status field in the
status array. The base address of the status array is stored in the TxStatus register, and
must be aligned on a 4 byte address boundary. During operation (when the transmit data
path is enabled) the TxDescriptor, TxStatus, and TxDescriptorNumber registers should
not be modified.
The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range"
error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the
received frame.
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
depicts the layout of the transmit descriptors in memory.
PACKET
PACKET
PACKET
PACKET
PACKET
PACKET
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
DATA BUFFER
DATA BUFFER
DATA BUFFER
DATA BUFFER
DATA BUFFER
DATA BUFFER
TxStatus
Chapter 10: LPC17xx Ethernet
StatusInfo
StatusInfo
StatusInfo
StatusInfo
StatusInfo
StatusInfo
UM10360
© NXP B.V. 2010. All rights reserved.
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