LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 369

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 332. Transfer Identifier register when FF = 1
Table 333. CAN Transmit Data register A (CAN1TDA[1/2/3] - address 0x4004 40[38/48/58], CAN2TDA[1/2/3] - address
Table 334. CAN Transmit Data register B (CAN1TDB[1/2/3] - address 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - address
UM10360
User manual
Bit
28:0
31:29 -
Bit
7:0
15;8
23:16 Data 3
31:24 Data 4
Bit
7:0
15;8
23:16 Data 7
31:24 Data 8
Symbol
ID
Symbol
Data 1
Data 2
Symbol
Data 5
Data 6
0x4004 80[38/48/58]) bit description
0x4004 80[3C/4C/5C]) bit description
16.7.15 CAN Transmit Data register A (CAN1TDA[1/2/3] - 0x4004 40[38/48/58],
16.7.16 CAN Transmit Data register B (CAN1TDB[1/2/3] -
16.7.17 CAN Sleep Clear register (CANSLEEPCLR - 0x400F C110)
Function
The 29-bit Identifier to be sent in the next transmit message.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Function
If RTR = 0 and DLC
the first Data byte of the next transmit message.
If RTR = 0 and DLC
the 2nd Data byte of the next transmit message.
If RTR = 0 and DLC
the 3rd Data byte of the next transmit message.
If RTR = 0 and DLC
the 4th Data byte of the next transmit message.
Function
If RTR = 0 and DLC
5th Data byte of the next transmit message.
If RTR = 0 and DLC
6th Data byte of the next transmit message.
If RTR = 0 and DLC
7th Data byte of the next transmit message.
If RTR = 0 and DLC
8th Data byte of the next transmit message.
CAN2TDA[1/2/3] - 0x4004 80[38/48/58])
When the corresponding TBS bit in CANSR is 1, software can write to one of these
registers to define the first 1 - 4 data bytes of the next transmit message. The Data Length
Code defines the number of transferred data bytes. The first bit transmitted is the most
significant bit of TX Data Byte 1.
0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0x4004 80[3C/4C/5C])
When the corresponding TBS bit in CANSR is 1, software can write to one of these
registers to define the 5th through 8th data bytes of the next transmit message. The Data
Length Code defines the number of transferred data bytes. The first bit transmitted is the
most significant bit of TX Data Byte 1.
This register provides the current sleep state of the two CAN channels and provides a
means to restore the clocks to that channel following wake-up. Refer to
“Sleep mode”
≥
≥
≥
≥
≥
≥
≥
≥
0101 in the corresponding CANTFI, this byte is sent as the
0110 in the corresponding CANTFI, this byte is sent as the
1000 in the corresponding CANTFI, this byte is sent as the
0111 in the corresponding CANTFI, this byte is sent as the
0001 in the corresponding CANxTFI, this byte is sent as
0010 in the corresponding CANxTFI, this byte is sent as
0011 in the corresponding CANxTFI, this byte is sent as
0100 in the corresponding CANxTFI, this byte is sent as
for more information on the CAN sleep feature.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
Reset Value
0
NA
Reset Value RM Set
0
0
0
0
Reset Value RM Set
0
0
0
0
UM10360
© NXP B.V. 2010. All rights reserved.
Section 16.8.2
369 of 840
RM Set
X
X
X
X
X
X
X
X
X