LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 279

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
13.8.5 OTG Interrupt Clear Register (OTGIntClr - 0x5000 C10C)
13.8.6 OTG Status and Control Register (OTGStCtrl - 0x5000 C110)
Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt
register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in
OTGIntSt.
The OTGStCtrl register allows enabling hardware tracking during the HNP hand over
sequence, controlling the OTG timer, monitoring the timer count, and controlling the
functions mapped to port U1 and U2.
Time critical events during the switching sequence are controlled by the OTG timer. The
timer can operate in two modes:
Table 259. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description
Bit
1:0
3:2
4
5
6
7
8
9
1. Monoshot mode: an interrupt is generated at the end of TIMEOUT_CNT (see
2. Free running mode: an interrupt is generated at the end of TIMEOUT_CNT (see
Section 13.8.7 “OTG Timer Register (OTGTmr - 0x5000
OTGIntSt, and the timer will be disabled.
Section 13.8.7 “OTG Timer Register (OTGTmr - 0x5000
and the timer value is reloaded into the counter. The timer is not disabled in this
mode.
Symbol
PORT_FUNC
TMR_SCALE
TMR_MODE
TMR_EN
TMR_RST
-
B_HNP_TRACK
A_HNP_TRACK
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Description
Controls port function. Bit 0 is set or cleared by hardware
when B_HNP_TRACK or A_HNP_TRACK is set and
HNP succeeds. See
Timer scale selection. This field determines the duration
of each timer count.
00: 10 μ s (100 KHz)
01: 100 μ s (10 KHz)
10: 1000 μ s (1 KHz)
11: Reserved
Timer mode selection.
0: monoshot
1: free running
Timer enable. When set, TMR_CNT increments. When
cleared, TMR_CNT is reset to 0.
Timer reset. Writing one to this bit resets TMR_CNT to 0.
This provides a single bit control for the software to
restart the timer when the timer is enabled.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Enable HNP tracking for B-device (peripheral), see
Section
HNP_SUCCESS or HNP_FAILURE is set.
Enable HNP tracking for A-device (host), see
Section
HNP_SUCCESS or HNP_FAILURE is set.
13.9. Hardware clears this bit when
13.9. Hardware clears this bit when
Section
Chapter 13: LPC17xx USB OTG
13.9. Bit 1 is reserved.
C114)”), the TMR bit is set in
C114)”), the TMR bit is set,
UM10360
© NXP B.V. 2010. All rights reserved.
279 of 840
Reset
Value
-
0x0
0
0
0
NA
0
0