LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 805

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 122. GPIO Interrupt Clear register for port 0 (IO0IntClr
Table 123. GPIO Interrupt Clear register for port 0 (IO2IntClr
Table 124. Ethernet acronyms, abbreviations, and
Table 125. Example PHY Devices. . . . . . . . . . . . . . . . . .147
Table 126. Ethernet RMII pin descriptions. . . . . . . . . . . .147
Table 127. Ethernet MIIM pin descriptions . . . . . . . . . . .147
Table 128. Ethernet register definitions . . . . . . . . . . . . . .148
Table 129. MAC Configuration register 1 (MAC1 - address
Table 130. MAC Configuration register 2 (MAC2 - address
Table 131. Pad operation . . . . . . . . . . . . . . . . . . . . . . . .152
Table 132. Back-to-back Inter-packet-gap register (IPGT -
Table 133. Non Back-to-back Inter-packet-gap register
Table 134. Collision Window / Retry register (CLRT - address
Table 135. Maximum Frame register (MAXF - address
Table 136. PHY Support register (SUPP - address
Table 137. Test register (TEST - address 0x5000 ) bit
Table 138. MII Mgmt Configuration register (MCFG - address
Table 139. Clock select encoding . . . . . . . . . . . . . . . . . .154
Table 140. MII Mgmt Command register (MCMD - address
Table 141. MII Mgmt Address register (MADR - address
Table 142. MII Mgmt Write Data register (MWTD - address
Table 143. MII Mgmt Read Data register (MRDD - address
Table 144. MII Mgmt Indicators register (MIND - address
Table 145. Station Address register (SA0 - address
Table 146. Station Address register (SA1 - address
Table 147. Station Address register (SA2 - address
Table 148. Command register (Command - address
Table 149. Status register (Status - address 0x5000 0104) bit
Table 150. Receive Descriptor Base Address register
Table 151. receive Status Base Address register (RxStatus -
Table 152. Receive Number of Descriptors register
UM10360
User manual
- 0x4002 808C)) bit description . . . . . . . . . . .138
- 0x4002 80AC) bit description . . . . . . . . . . . .139
definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
0x5000 0000) bit description . . . . . . . . . . . . .150
0x5000 0004) bit description . . . . . . . . . . . . .151
address 0x5000 0008) bit description. . . . . . .152
(IPGR - address 0x5000 000C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .152
0x5000 0010) bit description . . . . . . . . . . . . .153
0x5000 0014) bit description . . . . . . . . . . . . .153
0x5000 0018) bit description . . . . . . . . . . . . .153
description . . . . . . . . . . . . . . . . . . . . . . . . . . .154
0x5000 0020) bit description . . . . . . . . . . . . .154
0x5000 0024) bit description . . . . . . . . . . . . .155
0x5000 0028) bit description . . . . . . . . . . . . .155
0x5000 002C) bit description . . . . . . . . . . . . .156
0x5000 0030) bit description . . . . . . . . . . . . .156
0x5000 0034) bit description . . . . . . . . . . . . .156
0x5000 0040) bit description . . . . . . . . . . . . .157
0x5000 0044) bit description . . . . . . . . . . . . .157
0x5000 0048) bit description . . . . . . . . . . . . .157
0x5000 0100) bit description . . . . . . . . . . . . .158
description . . . . . . . . . . . . . . . . . . . . . . . . . . .158
(RxDescriptor - address 0x5000 0108) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .159
address 0x5000 010C) bit description . . . . . .159
(RxDescriptor - address 0x5000 0110) bit
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table 153. Receive Produce Index register
Table 154. Receive Consume Index register
Table 155. Transmit Descriptor Base Address register
Table 156. Transmit Status Base Address register (TxStatus
Table 157. Transmit Number of Descriptors register
Table 158. Transmit Produce Index register
Table 159. Transmit Consume Index register
Table 160. Transmit Status Vector 0 register (TSV0 -
Table 161. Transmit Status Vector 1 register (TSV1 - address
Table 162. Receive Status Vector register (RSV - address
Table 163. Flow Control Counter register
Table 164. Flow Control Status register (FlowControlStatus -
Table 165. Receive Filter Control register (RxFilterCtrl -
Table 166. Receive Filter WoL Status register
Table 167. Receive Filter WoL Clear register
Table 168. Hash Filter Table LSBs register (HashFilterL -
Table 169. Hash Filter MSBs register (HashFilterH - address
Table 170. Interrupt Status register (IntStatus - address
Table 171. Interrupt Enable register (intEnable - address
Table 172. Interrupt Clear register (IntClear - address
Table 173. Interrupt Set register (IntSet - address
Table 174. Power-Down register (PowerDown - address
Table 175. Receive Descriptor Fields . . . . . . . . . . . . . . . 173
Table 176. Receive Descriptor Control Word . . . . . . . . . 173
Table 177. Receive Status Fields . . . . . . . . . . . . . . . . . . 173
Table 178. Receive Status HashCRC Word . . . . . . . . . . 174
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
(RxProduceIndex - address 0x5000 0114) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
(RxConsumeIndex - address 0x5000 0118) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
(TxDescriptor - address 0x5000 011C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
- address 0x5000 0120) bit description . . . . . 161
(TxDescriptorNumber - address 0x5000 0124) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
(TxProduceIndex - address 0x5000 0128) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
(TxConsumeIndex - address 0x5000 012C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
address 0x5000 0158) bit description . . . . . . 163
0x5000 015C) bit description . . . . . . . . . . . . . 164
0x5000 0160) bit description . . . . . . . . . . . . . 164
(FlowControlCounter - address 0x5000 0170) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
address 0x5000 0174) bit description . . . . . . 165
address 0x5000 0200) bit description . . . . . . 166
(RxFilterWoLStatus - address 0x5000 0204) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
(RxFilterWoLClear - address 0x5000 0208) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
address 0x5000 0210) bit description . . . . . . 167
0x5000 0214) bit description . . . . . . . . . . . . . 168
0x5000 0FE0) bit description . . . . . . . . . . . . . 168
0x5000 0FE4) bit description . . . . . . . . . . . . . 169
0x5000 0FE8) bit description . . . . . . . . . . . . . 170
0x5000 0FEC) bit description. . . . . . . . . . . . . 170
0x5000 0FF4) bit description . . . . . . . . . . . . . 171
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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