LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 546
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
Fig 129.Quadrature Encoder Basic Operation
direction
position
PhA
PhB
26.4.1.2 Digital input filtering
26.4.2 Position capture
26.4.3 Velocity capture
-1 -1 -1 -1
Table 481. Encoder direction
Figure 129
All three encoder inputs (PhA, PhB, and index) require digital filtering. The number of
sample clocks is user programmable from 1 to 4,294,967,295 (0xFFFF FFFF). In order for
a transition to be accepted, the input signal must remain in new state for the programmed
number of sample clocks.
The capture mode for the position integrator can be set to update the position counter on
every edge of the PhA signal or to update on every edge of both PhA and PhB. Updating
the position counter on every PhA and PhB provides more positional resolution at the cost
of less range in the positional counter.
The position integrator and velocity capture can be independently enabled. Alternatively,
the phase signals can be interpreted as a clock and direction signal as output by some
encoders.
The position counter is automatically reset on one of two conditions. Incrementing past
the maximum position value (QEIMAXPOS) will reset the position counter to zero. If the
reset on index bit (
zero.
The velocity capture has a programmable timer and a capture register. It counts the
number of phase edges (using the same configuration as for the position integrator) in a
given time period. When the velocity timer (QEITIME) overflows the contents of the
velocity counter (QEIVEL) are transferred to the capture (QEICAP) register. The velocity
counter is then cleared. The velocity timer is loaded with the contents of the velocity
reload register (QEILOAD). Finally, the velocity interrupt (TIM_Int) is asserted. The
DIR bit
0
1
0
1
-1
-1
-1 -1 -1
shows how quadrature encoder signals equate to direction and count.
All information provided in this document is subject to legal disclaimers.
DIRINV bit
0
0
1
1
RESPI
+1 +1 +1 +1 +1 +1 +1 +1
Rev. 2 — 19 August 2010
) is set, sensing the index pulse will reset the position counter to
Chapter 26: LPC17xx Quadrature Encoder Interface (QEI)
direction
forward
reverse
reverse
forward
-1 -1 -1 -1
-1
-1
-1 -1 -1
-1
-1
UM10360
© NXP B.V. 2010. All rights reserved.
-1
-1 -1 -1
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