LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 804

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 67. Interrupt Priority Register 5 (IPR5 - 0xE000
Table 68. Interrupt Priority Register 6 (IPR6 - 0xE000
Table 69. Interrupt Priority Register 7 (IPR7 - 0xE000
Table 70. Interrupt Priority Register 8 (IPR8 - 0xE000
Table 71. Software Trigger Interrupt Register (STIR -
Table 72. Pin allocation table TFBGA100 package . . . . .92
Table 73. Pin description . . . . . . . . . . . . . . . . . . . . . . . . .95
Table 74. Summary of PINSEL registers . . . . . . . . . . . .104
Table 75. Pin function select register bits . . . . . . . . . . . .104
Table 76. Pin Mode Select register Bits . . . . . . . . . . . . .105
Table 77. Open Drain Pin Mode Select register Bits . . .105
Table 78. Pin Connect Block Register Map . . . . . . . . . .107
Table 79. Pin function select register 0 (PINSEL0 - address
Table 80. Pin function select register 1 (PINSEL1 - address
Table 81. Pin function select register 2 (PINSEL2 - address
Table 82. Pin function select register 3 (PINSEL3 - address
Table 83. Pin function select register 4 (PINSEL4 - address
Table 84. Pin function select register 7 (PINSEL7 - address
Table 85. Pin function select register 9 (PINSEL9 - address
Table 86. Pin function select register 10 (PINSEL10 -
Table 87. Pin Mode select register 0 (PINMODE0 - address
Table 88. Pin Mode select register 1 (PINMODE1 - address
Table 89. Pin Mode select register 2 (PINMODE2 - address
Table 90. Pin Mode select register 3 (PINMODE3 - address
Table 91. Pin Mode select register 4 (PINMODE4 - address
Table 92. Pin Mode select register 7 (PINMODE7 - address
Table 93. Pin Mode select register 9 (PINMODE9 - address
Table 94. Open Drain Pin Mode select register 0
Table 95. Open Drain Pin Mode select register 1
Table 96. Open Drain Pin Mode select register 2
Table 97. Open Drain Pin Mode select register 3
UM10360
User manual
E414) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
E418) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
E41C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
E420) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
0xE000 EF00) . . . . . . . . . . . . . . . . . . . . . . . . .90
0x4002 C000) bit description . . . . . . . . . . . . .108
0x4002 C004) bit description . . . . . . . . . . . . .108
0x4002 C008) bit description . . . . . . . . . . . . .109
0x4002 C00C) bit description . . . . . . . . . . . .109
0x4002 C010) bit description . . . . . . . . . . . . . 110
0x4002 C01C) bit description . . . . . . . . . . . . 111
0x4002 C024) bit description . . . . . . . . . . . . . 111
address 0x4002 C028) bit description . . . . . . 111
0x4002 C040) bit description . . . . . . . . . . . . . 112
0x4002 C044) bit description . . . . . . . . . . . . . 112
0x4002 C048) bit description . . . . . . . . . . . . . 113
0x4002 C04C) bit description . . . . . . . . . . . . . 113
0x4002 C050) bit description . . . . . . . . . . . . . 114
0x4002 C05C) bit description . . . . . . . . . . . . . 115
0x4002 C064) bit description . . . . . . . . . . . . . 115
(PINMODE_OD0 - address 0x4002 C068) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
(PINMODE_OD1 - address 0x4002 C06C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
(PINMODE_OD2 - address 0x4002 C070) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
(PINMODE_OD3 - address 0x4002 C074) bit
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Rev. 2 — 19 August 2010
Table 98. Open Drain Pin Mode select register 4
Table 99. I2C Pin Configuration register (I2CPADCFG -
Table 100. GPIO pin description . . . . . . . . . . . . . . . . . . . 121
Table 101. GPIO register map (local bus accessible registers
Table 102. GPIO interrupt register map . . . . . . . . . . . . . 123
Table 103. Fast GPIO port Direction register FIO0DIR to
Table 104. Fast GPIO port Direction control byte and
Table 105. Fast GPIO port output Set register (FIO0SET to
Table 106. Fast GPIO port output Set byte and half-word
Table 107. Fast GPIO port output Clear register (FIO0CLR to
Table 108. Fast GPIO port output Clear byte and half-word
Table 109. Fast GPIO port Pin value register (FIO0PIN to
Table 110. Fast GPIO port Pin value byte and half-word
Table 111. Fast GPIO port Mask register (FIO0MASK to
Table 112. Fast GPIO port Mask byte and half-word
Table 113. GPIO overall Interrupt Status register (IOIntStatus
Table 114. GPIO Interrupt Enable for port 0 Rising Edge
Table 115. GPIO Interrupt Enable for port 2 Rising Edge
Table 116. GPIO Interrupt Enable for port 0 Falling Edge
Table 117. GPIO Interrupt Enable for port 2 Falling Edge
Table 118. GPIO Interrupt Status for port 0 Rising Edge
Table 119. GPIO Interrupt Status for port 2 Rising Edge
Table 120. GPIO Interrupt Status for port 0 Falling Edge
Table 121. GPIO Interrupt Status for port 2 Falling Edge
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
(PINMODE_OD4 - address 0x4002 C078) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
address 0x4002 C07C) bit description. . . . . . 119
- enhanced GPIO features) . . . . . . . . . . . . . . 122
FIO4DIR - addresses 0x2009 C000 to 0x2009
C080) bit description . . . . . . . . . . . . . . . . . . . 123
half-word accessible register description . . . . 124
FIO4SET - addresses 0x2009 C018 to 0x2009
C098) bit description . . . . . . . . . . . . . . . . . . . 125
accessible register description. . . . . . . . . . . . 125
FIO4CLR- addresses 0x2009 C01C to 0x2009
C09C) bit description . . . . . . . . . . . . . . . . . . . 126
accessible register description. . . . . . . . . . . . 126
FIO4PIN- addresses 0x2009 C014 to 0x2009
C094) bit description . . . . . . . . . . . . . . . . . . . 128
accessible register description. . . . . . . . . . . . 128
FIO4MASK - addresses 0x2009 C010 to 0x2009
C090) bit description . . . . . . . . . . . . . . . . . . . 129
accessible register description. . . . . . . . . . . . 130
- address 0x4002 8080) bit description . . . . . 131
(IO0IntEnR - 0x4002 8090) bit description. . . 131
(IO2IntEnR - 0x4002 80B0) bit description . . 132
(IO0IntEnF - address 0x4002 8094) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
(IO2IntEnF - 0x4002 80B4) bit description. . . 134
Interrupt (IO0IntStatR - 0x4002 8084) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Interrupt (IO2IntStatR - 0x4002 80A4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Interrupt (IO0IntStatF - 0x4002 8088) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Interrupt (IO2IntStatF - 0x4002 80A8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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