LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 318

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

15.1 Basic configuration
15.2 Features
UM10360
User manual
The UART1 peripheral is configured using the following registers:
1. Power: In the PCONP register
2. Peripheral clock: In the PCLKSEL0 register
3. Baud rate: In register U1LCR
4. UART FIFO: Use bit FIFO enable (bit 0) in register U0FCR
5. Pins: Select UART pins through PINSEL registers and pin modes through the
6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U1LCR
7. DMA: UART1 transmit and receive functions can operated with the GPDMA controller
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UM10360
Chapter 15: LPC17xx UART1
Rev. 2 — 19 August 2010
Remark: On reset, UART1 is enabled (PCUART1 = 1).
registers DLL
needed, set the fractional baud rate in the fractional divider register
FIFO.
PINMODE registers
Remark: UART receive pins should not have pull-down resistors enabled.
This enables access to U1IER
the appropriate Interrupt Set Enable register.
(see
Full modem control handshaking available
Data sizes of 5, 6, 7, and 8 bits.
Parity generation and checking: odd, even mark, space or none.
One or two stop bits.
16 byte Receive and Transmit FIFOs.
Built-in baud rate generator, including a fractional rate divider for great versatility.
Supports DMA for both transmit and receive.
Auto-baud capability
Break generation and detection.
Multiprocessor addressing mode.
RS-485 support.
Table
543).
All information provided in this document is subject to legal disclaimers.
(Table
Rev. 2 — 19 August 2010
(Section
292) and DLM
8.5).
(Table
(Table
(Table
(Table
298), set bit DLAB =1. This enables access to
46), set bits PCUART1.
294). Interrupts are enabled in the NVIC using
293) for setting the baud rate. Also, if
(Table
40), select PCLK_UART1.
(Table
297) to enable
© NXP B.V. 2010. All rights reserved.
(Table
User manual
(Table
305).
318 of 840
298).