LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 839

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
34.3.1.6
34.3.2
34.3.2.1
34.3.2.2
34.3.2.3
34.3.2.4
34.3.2.5
34.3.2.5.1 Directly accessing an alias region . . . . . . . . 742
34.3.2.5.2 Directly accessing a bit-band region. . . . . . . 742
34.3.2.6
34.3.2.6.1 Little-endian format. . . . . . . . . . . . . . . . . . . . 743
34.3.2.7
34.3.2.8
34.3.3
34.3.3.1
34.3.3.2
34.3.3.3
34.3.3.4
34.3.3.5
34.3.3.6
34.3.3.7
34.3.3.7.1 Exception entry. . . . . . . . . . . . . . . . . . . . . . . 750
34.3.3.7.2 Exception return . . . . . . . . . . . . . . . . . . . . . . 751
34.3.4
34.3.4.1
34.3.4.2
34.3.4.3
34.3.4.4
34.3.5
34.3.5.1
34.3.5.1.1 Wait for interrupt . . . . . . . . . . . . . . . . . . . . . . 756
34.3.5.1.2 Wait for event . . . . . . . . . . . . . . . . . . . . . . . . 756
34.3.5.1.3 Sleep-on-exit . . . . . . . . . . . . . . . . . . . . . . . . 757
34.3.5.2
34.3.5.2.1 Wakeup from WFI or sleep-on-exit. . . . . . . . 757
34.3.5.2.2 Wakeup from WFE . . . . . . . . . . . . . . . . . . . . 757
34.3.5.3
34.3.5.4
34.4
34.4.1
34.4.2
34.4.2.1
34.4.2.2
34.4.2.3
34.4.2.4
UM10360
User manual
ARM Cortex-M3 User Guide: Peripherals . . 759
The Cortex Microcontroller Software Interface
Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Memory model . . . . . . . . . . . . . . . . . . . . . . . 737
Memory regions, types and attributes. . . . . . 737
Memory system ordering of memory
accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Behavior of memory accesses . . . . . . . . . . . 739
Software ordering of memory accesses . . . . 739
Bit-banding . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Memory endianness . . . . . . . . . . . . . . . . . . . 743
Synchronization primitives . . . . . . . . . . . . . . 743
Programming hints for the synchronization
primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Exception model . . . . . . . . . . . . . . . . . . . . . . 745
Exception states . . . . . . . . . . . . . . . . . . . . . . 745
Exception types . . . . . . . . . . . . . . . . . . . . . . 745
Exception handlers . . . . . . . . . . . . . . . . . . . . 747
Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . 748
Exception priorities . . . . . . . . . . . . . . . . . . . . 748
Interrupt priority grouping . . . . . . . . . . . . . . . 749
Exception entry and return . . . . . . . . . . . . . . 749
Fault handling . . . . . . . . . . . . . . . . . . . . . . . . 753
Fault types . . . . . . . . . . . . . . . . . . . . . . . . . . 753
Fault escalation and hard faults . . . . . . . . . . 754
Fault status registers and fault address
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
Lockup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
Power management . . . . . . . . . . . . . . . . . . . 756
Entering sleep mode. . . . . . . . . . . . . . . . . . . 756
Wakeup from sleep mode. . . . . . . . . . . . . . . 757
The Wake-up Interrupt Controller . . . . . . . . . 757
Power management programming hints. . . . 758
About the Cortex-M3 peripherals . . . . . . . . . 759
Nested Vectored Interrupt Controller . . . . . . 760
The CMSIS mapping of the Cortex-M3 NVIC
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
Interrupt Set-enable Registers . . . . . . . . . . . 761
Interrupt Clear-enable Registers. . . . . . . . . . 761
Interrupt Set-pending Registers . . . . . . . . . . 762
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
34.4.2.5
34.4.2.6
34.4.2.7
34.4.2.8
34.4.2.9
34.4.2.9.1 Hardware and software control of interrupts 765
34.4.2.10 NVIC design hints and tips. . . . . . . . . . . . . . 765
34.4.2.10.1 NVIC programming hints . . . . . . . . . . . . . . 766
34.4.3
34.4.3.1
34.4.3.2
34.4.3.2.1 About IT folding . . . . . . . . . . . . . . . . . . . . . . 768
34.4.3.3
34.4.3.4
34.4.3.5
34.4.3.6
34.4.3.6.1 Binary point . . . . . . . . . . . . . . . . . . . . . . . . . 772
34.4.3.7
34.4.3.8
34.4.3.9
34.4.3.9.1 System Handler Priority Register 1 . . . . . . . 775
34.4.3.9.2 System Handler Priority Register 2 . . . . . . . 775
34.4.3.9.3 System Handler Priority Register 3 . . . . . . . 775
34.4.3.10 System Handler Control and State Register 775
34.4.3.11 Configurable Fault Status Register . . . . . . . 777
34.4.3.11.1 Memory Management Fault Status Register 777
34.4.3.11.2 Bus Fault Status Register. . . . . . . . . . . . . . 778
34.4.3.11.3 Usage Fault Status Register . . . . . . . . . . . 779
34.4.3.12 Hard Fault Status Register. . . . . . . . . . . . . . 781
34.4.3.13 Memory Management Fault Address
34.4.3.14 Bus Fault Address Register . . . . . . . . . . . . . 781
34.4.3.15 System control block design hints and tips . 782
34.4.4
34.4.4.1
34.4.4.2
34.4.4.2.1 Calculating the RELOAD value . . . . . . . . . . 784
34.4.4.3
34.4.4.4
34.4.4.5
34.4.5
34.4.5.1
34.4.5.2
34.4.5.3
34.4.5.4
34.4.5.4.1 The ADDR field . . . . . . . . . . . . . . . . . . . . . . 790
34.4.5.5
34.4.5.5.1 SIZE field values . . . . . . . . . . . . . . . . . . . . . 791
Interrupt Clear-pending Registers . . . . . . . . 762
Interrupt Active Bit Registers . . . . . . . . . . . . 763
Interrupt Priority Registers . . . . . . . . . . . . . . 763
Software Trigger Interrupt Register . . . . . . . 764
Level-sensitive and pulse interrupts. . . . . . . 764
System control block . . . . . . . . . . . . . . . . . . 767
The CMSIS mapping of the Cortex-M3 SCB
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Auxiliary Control Register . . . . . . . . . . . . . . 767
CPUID Base Register . . . . . . . . . . . . . . . . . 768
Interrupt Control and State Register . . . . . . 768
Vector Table Offset Register . . . . . . . . . . . . 770
Application Interrupt and Reset Control
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
System Control Register . . . . . . . . . . . . . . . 772
Configuration and Control Register . . . . . . . 773
System Handler Priority Registers . . . . . . . . 774
Caution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
System timer, SysTick . . . . . . . . . . . . . . . . . 783
SysTick Control and Status Register . . . . . . 783
SysTick Reload Value Register . . . . . . . . . . 784
SysTick Current Value Register . . . . . . . . . . 784
SysTick Calibration Value Register . . . . . . . 784
SysTick design hints and tips. . . . . . . . . . . . 785
Memory protection unit . . . . . . . . . . . . . . . . 786
MPU Type Register . . . . . . . . . . . . . . . . . . . 787
MPU Control Register . . . . . . . . . . . . . . . . . 788
MPU Region Number Register . . . . . . . . . . 789
MPU Region Base Address Register. . . . . . 789
MPU Region Attribute and Size Register. . . 790
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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