mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 966

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

17.3.2 The PCMCIA Input Port Signals
The MPC823 provides synchronization, transition detection, optional interrupt generation
and a means for the software to read the signal state. This function is not necessarily
specific to PCMCIA and the signals can be used as a general-purpose input port with edge
detection and interrupt capability.
The following signals are used by a PCMCIA slot to indicate the status of the card. They
appear on the IP_B[0:7] pins, which you can access through bits 16-23 of the PIPR when
you are not operating the PCMCIA controller. All these signals are symmetrical, except for
IP_B7, which has extended edge detection capability, and IP_B2 that serves as IOIS16_B
cycle control signals for PCMCIA cycles.
• Voltage Sense (VS1_B, VS2_B)—Input. These signals are used as VS1 and VS2 and
• Write Protect (WP)—Input. When the card and its socket are programmed for memory
• Card Detect (CD2_B, CD1_B)—Input. These signals ensure that a card has been
• Battery Voltage Detect (BVD2_B, BVD1_B)—Input. When the card and its socket are
• Status Change (STSCHG)—Input. When the card and its socket are programmed for
are generated by PC cards. They notify the socket of the card’s V
signals are connected to the IP_B[0:1] pins.
interface operation, WP reflects the status of the write protect switch on the PC card. It
must be asserted by the PC card when the switch is enabled and negated when the
switch is disabled. For a PC card without a switch, this signal must be connected to
ground if the PC card can be written and connected to system V
permanently write-protected. This signal is connected to the IP_B2 pin.
inserted properly. They must be connected to ground internally on the PC card and they
will be forced low whenever a card is placed in the socket. These signals must be pulled
up to system V
down. These signals are connected to the IP_B3 and IP_B4 pins, respectively.
programmed for memory interface operation, these signals are generated by PC cards
with an onboard battery. They report the battery’s condition. Both BVD1_B and
BVD2_B must be held asserted when the battery is in good condition. Negating
BVD2_B while keeping BVD1_B asserted indicates the battery is in a warning condition
and must be replaced, although data integrity on the card is still assured. Negating
BVD1_B indicates that the battery is no longer serviceable and data is lost, regardless
of the state of BVD2_B. These signals are connected to the IP_B5 and IP_B6 pins,
respectively.
I/O Interface operation, the BVD1_B signal is used as STSCHG, it is generated by the
I/O PC card. The STSCHG signal must be held negated when the Signal on Change bit
and Changed bit in the card status register on the PC card are set to zero. The STSCHG
signal must be asserted when both bits are set to one.
CC
to allow card detection to function while the card socket is powered
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
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CC
CC
requirement. These
if the PC card is
PCMCIA Interface
17-5