mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 275

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
System Interface Unit
Notice that the core takes the system reset interrupt when a nonmaskable interrupt is
asserted and the external interrupt when any other interrupt is asserted by the interrupt
controller. Each one of the external IRQx pins has its own dedicated assigned priority level
and there are eight additional interrupt priority levels. Each one of the system interface unit
internal interrupt sources (the interrupt request that is generated by the communication
processor module’s interrupt controller) can be assigned by the software to any one of those
eight interrupt priority levels. Thus, a very flexible interrupt scheme is realized.
12.3.2 Priority of the Interrupt Sources
The system interface unit has 15 interrupt sources that assert just one interrupt request to
the core. There are seven external IRQx pins and eight interrupt levels. The priority between
all interrupt sources is shown in Table 12-1.
NUMBER
16-31
Table 12-1. Priority of System Interface Unit Interrupt Sources
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Note: IRQ0 is a nonmaskable interrupt. It will cause the core to go to the system reset
vector.
Freescale Semiconductor, Inc.
PRIORITY
Highest
LEVEL
Lowest
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
INTERRUPT SOURCE
DESCRIPTION
Reserved
Level 0
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
INTERRUPT CODE
00000000
00000100
00001000
00001100
00010000
00010100
00011000
00011100
00100000
00100100
00101000
00101100
00110000
00110100
00111000
00111100
MOTOROLA

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