mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 863

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Once the REN bit is set in the SMCMR, the first time-slot after frame sync causes the SMCx
receiver to achieve synchronization. Data is received immediately, but only during the
defined receive time-slots. The receiver continues receiving data during its defined
time-slots until you clear the REN bit. If the ENTER HUNT MODE command is issued, the
receiver loses synchronization, closes the current buffer, and resynchronizes to the first
time-slot after the frame sync.
Once the TEN bit is set in the SMCMR, an SMCx Transparent controller waits for the
transmit FIFO to be loaded before trying to achieve synchronization. Once the transmit FIFO
is loaded, synchronization and transmission begins, depending on the following situations:
If an SMCx Transparent controller runs out of transmit buffers and a new transmit buffer is
provided later, idles are transmitted during the gap between data buffers. Data transmission
from the later data buffer begins at the beginning of an SMCx Transparent controller
time-slot, but not necessarily the first time-slot after the frame sync. So if you want to
maintain a certain bit alignment beginning with the first time-slot, make sure that at least one
TX buffer descriptor is always ready and that no underrun occurs. Otherwise, the SMCx
Transparent transmitter must be disabled and reenabled. Refer to
Section 16.11.5 Disabling the SMCs On-the-Fly for a description of how to safely disable
and reenable the SMCx Transparent controller. Simply clearing and setting TEN may not be
sufficient.
• If a buffer is made ready when an SMCx Transparent controller is enabled, then the first
• If a buffer has an SMCx Transparent controller enabled, then the first byte in the next
• If a buffer is ended with the L bit set, then the next buffer can appear in any time-slot
byte will be placed in time-slot 1 if the CLEN field in SMCMR is set to 8 and slot 2 if
CLEN is set to 16.
buffer can appear in any time-slot associated with this channel.
associated with this channel.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
16-411

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