mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 322

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
External Bus Interface
13.4.3 Burst Transfers
The MPC823 uses burst transfers to access 16-byte operands. A burst accesses a block of
16 bytes that must be aligned to a 16-byte memory boundary by supplying a starting address
that points to the critical words and requiring the memory device to sequentially drive/sample
each word on the data bus. The selected slave device must internally increment the external
A[28:29] signal (or A30 for a 16-bit port size slave device) of the supplied address for each
transfer, thus causing the address to wrap around at the end of the 4-word block. The
address and transfer attributes supplied by the MPC823 remain stable during the transfers
and the selected device terminates each transfer by driving/sampling the word on the data
bus and asserting the TA signal.
The MPC823 also supports burst-inhibited transfers for slave devices that are unable to
support bursting. For this type of bus cycle, the selected slave device supplies/samples the
first word the MPC823 points to and asserts the BI signal with TA for the first transfer of the
burst access. The MPC823 responds by terminating the burst and accessing the remainder
of the 16-byte block, thus using three read/write cycle bus (each one for a word) for a 32-bit
port width slave, seven read/write cycle bus for a 16-bit port width slave, or fifteen read/write
cycle bus for an 8-bit port width slave.
Burst transfers assume that the external memory has a 32-bit port size. The MPC823
provides an effective mechanism for interfacing with 16- and 8-bit port size memories that
allow burst transfers to these devices when they are controlled by the internal memory
controller. The MPC823 attempts to initiate a burst transfer as normal. If the slave device
responds to a cycle prior to the TA signal for the first beat, its port size is 8 or 16 bits and the
MPC823 completes a burst of 8- or 16-bit beats. Effectively, each of the data beats of the
burst transfers only 1 or 2 bytes. This 8- or 16-beat burst is also considered an atomic
transaction, so the MPC823 will not allow other unrelated master accesses or bus arbitration
to intervene between the transfers.
13.4.4 The Burst Mechanism
The MPC823 burst mechanism consists of one signal indicating that the cycle is a burst
cycle, one indicating the duration of the burst data, and another signal indicating whether
the slave is burstable. These signals are in addition to the basic signals of the bus. At the
start of the burst transfer, the master drives the address, address attributes, and BURST
signal to indicate that a burst transfer is being initiated, along with the assertion of the TS
signal. If the slave is burstable, it negates the BI signal. If the slave cannot burst, it must
assert the BI signal. During the data phase of a burst write cycle the master drives the data.
It also asserts the BDIP signal if it intends to drive a subsequent data beat after the current
data beat. When the slave has received the data, it asserts the TA signal to let the master
know it is ready for the next data transfer. The master again drives the next data and asserts
or negates the BDIP signal. If the master does not intend to drive another data beat after the
current one, it negates the BDIP signal to let the slave know that the next subsequent data
beat transfer is the last data of the burst write transfer. During the data phase of a burst read
cycle, the master receives data from the addressed slave. If the master needs more than
one data, it asserts the BDIP signal. When the data is received prior to the last data, the
master negates the BDIP signal. Thus, the slave stops driving new data after it receives the
negation of the BDIP signal at the rising edge of the clock. See Figure 13-10 for details.
MPC823 REFERENCE MANUAL
MOTOROLA
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