mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 116

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Notice that GCLK1_50, GCLK2_50, and CLKOUT can have a lower frequency than GCLK1
and GCLK2. This allows the external bus to operate at lower frequencies as controlled by
the EBDF bit in the SCCR. GCLK2_50 always rises simultaneously with GCLK2. GCLK1_50
rises simultaneously with GCLK1, but when the MPC823 is not in normal low mode, the
falling edge of GCLK1_50 occurs in the middle of the high phase of GCLK2_50 and EBDF
determines the division factor between GCLKx and GCLKx_50. See Figure 5-9 for more
information.
The general system clock defaults to VCOOUT frequency at system reset. In normal low
mode, the frequency of the general system clock can be dynamically switched using the
SCCR.
You can switch the general system clock division factor between two different values (DFNH
and DFNL). The high frequency is generated by using the DFNH field in the SCCR and it is
used in normal high and doze high mode. The low frequency is generated using the DFNL
field in the SCCR and it is used in normal low and doze low mode. Conventionally, to
conserve power low frequency is slower than high frequency.
In some applications, a high frequency is needed to perform critical tasks. For example,
interrupt routines need to be run at a high frequency, but the rest of the application can run
at a low frequency to conserve power. The MPC823 can automatically switch between low
and high frequency operation when one of the following conditions exist:
• A pending interrupt from the interrupt controller occurs. This option is maskable by the
• The POW bit of the machine status register is clear. This option is maskable by the
• The RISC microcontroller in the communication processor module has a pending
PRQEN bit in the SCCR.
PRQEN bit in the SCCR.
request or is currently executing a routine. This option is maskable by the CRQEN bit
in the SCCR.
VCOOUT
Figure 5-7. Selecting the General System Clock
Freescale Semiconductor, Inc.
For More Information On This Product,
DFNH DIVIDER
DFNL DIVIDER
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
LOW POWER MODE
DFNH
DFNL
MUX
2:1
Clocks and Power Control
GCLK1
5-17