mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 874

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.11.7.16 HANDLING INTERRUPTS IN THE SMCx. Follow these steps to handle an
interrupt in the serial management controller:
16.11.8 The SMCx in GCI Mode
The serial management controllers can be used to control the circuit interface and monitor
channels of the general circuit interface (GCI) frame. When using the SCIT configuration of
a general circuit interface, one serial management controller can handle SCIT channel 0,
and the other serial management controller can handle SCIT channel 1. The main features
of a serial management controller in GCI mode are as follows:
7. Initialize the TX buffer descriptor and assume the TX data buffer is at 0x00002000 in
8. Write 0xFF to the SMCE–Transparent register to clear any previous events.
9. Write 0x13 to the SMCM–Transparent register to enable all possible serial
10. Write 0x00000010 to the CIMR so that SMC1 can generate a system interrupt. The
11. Write 0x3830 to the SMCMR–Transparent to configure 8-bit characters, unreversed
12. Write 0x3833 to the SMCMR–Transparent to enable the SMC1 transmitter and
1. Once an interrupt occurs, read the SMCE register to discover the cause of the
2. Process the TX buffer descriptor to reuse it if the TX bit is set in the SMCE–
3. Clear the SMC1 bit in the CISR.
4. Execute the rfi instruction.
• Each SMCx channel supports the circuit interface and monitor channels of the GCI
• Two serial management controllers support the two sets of circuit interface and monitor
• Full-duplex operation
• Local loopback and echo capability for testing
(IOM-2) in ISDN applications
channels in SCIT channels 0 and 1
main memory and contains five 8-bit characters. Write 0xB000 to TX_BD_Status,
0x0005 to TX_BD_Length, and 0x00002000 to TX_BD_Pointer.
management controller interrupts.
CICR must also be initialized.
data, and normal operation (not loopback). Notice that the transmitter and receiver are
not enabled yet.
receiver. This additional write ensures that the TEN and REN bits are enabled last.
interrupts. The SMCE bits are usually cleared at this time.
Transparent register. Extract data from the RX buffer descriptor if the RX bit is set in
the SMCE–Transparent register. To transmit another buffer, simply set the R bit in the
RX buffer descriptor.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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