mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1036

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Video Controller
19.3.3 Video Command Register
The 8-bit video command register (VCMR) is used to control the display format.
Bits 0–5—Reserved
These bits are reserved and must be set to 0.
ASEL—Active Set Select
This bit selects one RAM array and FIFO control register set to be active for the next frame.
The current set selection is reflected in the CAS bit of the VSR.
BD—Blank Display
When set, this bit forces the background video to be displayed and flushes the current FIFO.
VCMR
RESET
FIELD
ADDR
R/W
BIT
0 = Selects RAM_0 and FIFO register set_0 as the active set.
1 = Selects RAM_1 and FIFO register set_1 as the active set.
0 = Display the image from the frame buffer.
1 = Force background video and flush FIFO.
0
Note: Once the ASEL bit is changed, you cannot access video RAM until the CAS bit
in the VSR reflects the change.
Freescale Semiconductor, Inc.
1
For More Information On This Product,
MPC823 REFERENCE MANUAL
2
Go to: www.freescale.com
RESERVED
R/W
(IMMR & 0xFFFF0000) + 0x806
0
3
4
5
ASEL
R/W
6
0
MOTOROLA
R/W
BD
7
0

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