mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 94

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Reset
4.3 HOW TO CONFIGURE RESET
In normal operation, you can configure reset with a hard reset. However, to configure the
development port you must use a soft reset.
4.3.1 Hard Reset
When a hard reset event occurs, the MPC823 reconfigures its hardware system as well as
the development port configuration. The logical value of the bits that determine its initial
mode of operation are sampled either from the data bus or from an internal default constant
(D[0:31]=x’00000000). If, at sampling time, RSTCONF is asserted, the configuration is
sampled from the data bus. Otherwise, it is sampled from the internal default. While
HRESET and RSTCONF are asserted, the MPC823 pulls the data bus low through a weak
resistor (2-4k). You can overwrite this default by driving high to the appropriate bit, as shown
in Figure 4-1. Figures 4-2 through 4-4 illustrate how reset configuration works when
PORESET is asserted. While the PORESET input signal is being asserted, the core
assumes the default reset configuration that changes when PORESET is negated or the
CLKOUT signal starts oscillating. In this last case, the hardware configuration is sampled
every nine clock cycles on the rising edge of the CLKOUT. The setup time required for the
data bus is 15 cycles and the maximum rise time of HRESET must be less than six clock
cycles. For more information, see Section 4.3.2 Soft Reset .
MPC823
MUX
CONFIGURATION
WORD
DX (DATA LINE)
HRESET
RSTCONF
Figure 4-1. Reset Configuration Basic Scheme
MPC823 REFERENCE MANUAL
4-7
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