mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1236

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

lwarx
Assembly Syntax
Definition
Operation
Description
FIELD
FIELD
BIT
BIT
16
0
17
1
18
B
2
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For More Information On This Product,
19
3
else b
EA
RESERVE
RESERVE_ADDR
rD
EA is loaded into rD.
This instruction creates a reservation for use by a store word
conditional indexed (stwcx.) instruction. The physical address
computed from EA is associated with the reservation, and
replaces any address previously associated with the reservation.
EA must be a multiple of four. If it is not, either the system
alignment exception handler is invoked or the results are
boundedly undefined. When the RESERVE bit is set, the
processor enables hardware snooping for the block of memory
addressed by the RESERVE address.
If the processor detects that another processor writes to the
block of memory it has reserved, it clears the RESERVE bit. The
stwcx. instruction will only do a store if the RESERVE bit is set.
The stwcx. instruction sets the CR0[EQ] bit if the store was
successful and clears it if it failed. The lwarx and stwcx.
combination can be used for atomic read-modify-write
sequences.
lwarx
Load Word and Reserve Indexed
if rA = 0 then b
EA is the sum (rA|0) + (rB). The word in memory addressed by
20
MPC823 REFERENCE MANUAL
4
MEM(EA,4)
b + (rB)
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21
(rA)
5
rD,rA,rB
22
1
6
0
23
7
physical_addr(EA)
24
D
8
25
9
20
10
26
MPC823 Instruction Set—lwarx
11
27
12
28
13
29
A
14
30
B-83
15
31
0