mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 669

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
TPM—Transmitter Parity Mode
This field selects the type of parity that the transmitter performs. It can be modified
on-the-fly.
16.9.15.16 SCCx UART RECEIVE BUFFER DESCRIPTORS. On a per-buffer basis, the
communication processor module uses the receive (RX) buffer descriptors to report
information about the received data. The communication processor module closes the
current buffer, generates a maskable interrupt, and starts receiving data into the next buffer
after one of the following events occur:
An address character is received in multidrop mode and is written to the next buffer for a
software comparison.
An example of the RX buffer descriptor process is illustrated in Figure 16-74.
• A user-defined control character is received.
• An error occurs during message processing.
• A full receive buffer is detected.
• A MAX_IDL number of consecutive idle characters is received.
• The ENTER HUNT MODE command is issued.
• The CLOSE RX BD command is issued.
00 = Odd parity.
01 = Force low parity. Always send a zero in the parity bit position.
10 = Even parity.
11 = Force high parity. Always send a one in the parity bit position.
Note: The receive parity errors can be ignored, but not disabled.
Note: The communication processor module sets all the status bits in this buffer
descriptor, but you must clear them before submitting the buffer descriptor to the
communication processor module.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
16-217

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