mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 362

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Memory Controller
The two user-programmable machines (UPMA and UPMB) in the memory controller provide
a flexible interface to many types of memory devices. Each UPM can control the address
multiplexing necessary to access DRAM devices, the timing of the BS signals, and the
timing of the GPLx signals. Each memory bank can be assigned to either UPM. There are
a total of eight CSx signals that can be split between the two UPMs.
Each user-programmable machine is a RAM-based machine controlled by software. The
software toggles the memory controller external signals when an external single word
read/write access or an external burst read/write access is initiated by an internal or external
master. The UPM also controls address multiplexing, address increment, and transfer
acknowledge assertion for a specific memory access. The UPM can be programmed to run
a specific signal pattern for a certain duration of clock cycles. At every clock cycle, the logical
value of the external signals specified in the RAM array is output on the corresponding UPM
pins.
When a new access to external memory is requested by any of the internal or external
masters, the address of the transfer and the address type is compared to each one of the
valid banks defined in the memory controller. Notice that all of the A[0:16] and AT[0:2]
signals are maskable. When an address match is found in one of the memory bank
chip-select ranges, the corresponding MS field in the base register defines the machine that
handles the memory access. See Figure 15-4 for details.
The memory controller provides four parity (DP[0:3]) signals, one for each data byte lane on
the MPC823 system bus. The parity on the bus is only checked if the memory bank
accessed in the current transaction has parity enabled. Parity checking/generation can be
enabled for a specific memory bank in the base register. The type of parity is defined in the
system interface unit module configuration register, which is explained in
Section 12.12.1.1 SIU Module Configuration Register . Also, system protection is
provided by defining each memory bank as read-only or read/write.
MPC823 REFERENCE MANUAL
MOTOROLA
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