mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 430

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Memory Controller
An asynchronous example interconnection in which an external master and the MPC823
can both share access to a DRAM bank is illustrated in Figure 15-39. Notice that CS1,
UPMA, and GPL_A5 were chosen to assist in the control of DRAM bank accesses.
Figure 15-40 illustrates the timing behavior of the GPL_A5 and other control signals when
an external master to a DRAM bank initiates a single beat read access. The state of the
GPL_A5 pin in the first clock cycle of the memory device access is determined by the value
of the G5LS bit in the corresponding option register.
Figure 15-39. Asynchronous External Master Interconnect Example
CS1
BSx
GPL_A5
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
A[6:31]
D[0:31]
R/W
AS
TSIZx
TA
BB
BR
BG
Go to: www.freescale.com
MULTIPLEXER
DRAM
EXTERNAL
EXTERNAL
ARBITER
MASTER
ARBITRATION
SIGNALS
MOTOROLA

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