mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1082

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

The processor enters into the debug mode state when at least one of the bits in the ICR is
set, the corresponding bit in the DER is enabled, and debug mode is enabled. When debug
mode is enabled and an enabled event occurs, the processor waits until its pipeline is empty
and then starts fetching the next instructions from the development port. For information on
the exact value of the SRR0 and SRR1 registers, refer to Section 7.3.7.3 Definitions.
When the processor is in debug mode, the freeze indication is asserted, thus allowing any
properly programmed peripheral to stop. The fact that the core is in debug mode is also
broadcasted to the external world using the value b’11’ on the VFLS pins. The freeze signal
can be asserted by the software when debug mode is disabled. The development port must
read the value of the ICR to discover the cause of debug mode entry. Reading the ICR clears
all of its bits.
20.4.2.3 CHECKSTOP STATE AND DEBUG MODE. The core enters checkstop state if
the machine check interrupt is disabled (MSR
detected. However, if a machine check interrupt is detected when MSR
is enabled, the checkstop enable bit in the DER is set, and the core enters debug mode
rather than the checkstop state. The various actions taken by the core when a machine
check interrupt is detected are provided in the following table.
NOTES:
ENABLE
• Peripheral breakpoint from the development port generated by external modules are
• Development port nonmaskable interrupt occurs as a result of a debug station request.
DEBUG
MODE
recognized only when MSR
Useful in some catastrophic events, such as an endless loop when MSR
result of this event, the machine can enter a nonrestartable state.
0
0
1
1
1
1
1.
2.
The checkstop enable bit of the DER register.
The machine check interrupt enable bit of the DER register.
MSR
0
1
0
0
1
1
ME
Table 20-7. Checkstop State and Debug Mode
Freescale Semiconductor, Inc.
CHSTPE
For More Information On This Product,
X
X
X
X
0
1
1
MPC823 REFERENCE MANUAL
RI
=1.
Go to: www.freescale.com
MCIE
X
X
X
X
0
1
2
ACTION PERFORMED BY THE CORE
Branch to the Machine Check Interrupt
Branch to the Machine Check Interrupt
CHECK INTERRUPT IS DETECTED
ME
=0) and a machine check interrupt is
Enter Checkstop State
Enter Checkstop State
WHEN A MACHINE
Enter Debug Mode
Enter Debug Mode
Development Capabilities and Interface
ME
=0, debug mode
RI
0x20000000
0x10000000
0x20000000
0x20000000
0x10000000
0x10000000
=0. As a
VALUE
ICR
20-27