mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 396

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Memory Controller
15.5 USER-PROGRAMMABLE MACHINES
Each of the two user-programmable machines (UPMs) is a flexible interface that connects
to a wide range of memory devices. At the heart of each UPM is an internal memory RAM
array that specifies the logical value driven on the external memory controller pins for a
given clock cycle. Each word in the RAM array provides bits that allow a memory access to
be controlled with a resolution of one quarter of the system clock period on the byte-select
and chip-select lines. Figure 15-20 illustrates the basic operation of each UPM. A UPM cycle
is initiated when:
The RAM array contains 32-bit entries referred to as RAM words. If the UPM reads a RAM
word with the WAEN bit set, the external UPWAITx signal is sampled and synchronized by
the memory controller and the current request is frozen. The signal timing generator will load
the RAM word from the RAM array to drive the general-purpose lines, byte-selects, and
chip-selects.
INTERNAL/EXTERNAL MEMORY
ACCESS REQUEST
• Any internal or external master requests an external memory access
• A memory periodic timer expires and requests a transaction
• A transfer error or reset generates an exception request
• The memory command register receives a RUN command (software) from the CPU
UPWAIT
EXCEPTION REQUEST
MEMORY PERIODIC TIMER
REQUEST
SOFTWARE REQUEST
Figure 15-20. User-Programmable Machine Block Diagram
REQUEST
LOGIC
WAIT
Freescale Semiconductor, Inc.
HOLD
For More Information On This Product,
MPC823 REFERENCE MANUAL
GENERATOR
WAEN BIT
Go to: www.freescale.com
ARRAY
INDEX
INCREMENT
INDEX
(LAST = 0)
INDEX
INTERNAL CONTROLS
INTERNAL
SIGNALS
LATCH
ARRAY
RAM
TIMING GENERATOR
SIGNALS
GPLx, BSx, CSx
MOTOROLA