mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 822

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.10.8.6 USB ENDPOINT CONFIGURATION REGISTERS 0–3. There are four 16-bit,
memory-mapped, read/write USB endpoint configuration (USEPx) registers.
EPN— Endpoint Number
This field defines the supported endpoint number. It is used in slave mode and ignored in
host mode.
Bits 4–5 and 8–9—Reserved
These bits are reserved and must be set to 0.
TM—Transfer Mode
MF—Enable Multi-Frame
This bit allows loading of the next transmit packet into the FIFO before the previous packet
finishes transmitting. This bit must be set to zero, unless the endpoint is configured for
isochronous transfer mode or the endpoint is configured as a host (endpoint 0 only).
RTE—Retransmit Enable
This bit must be set to zero for an endpoint configured for isochronous transfer mode.
USEP0–USEP3
RESET
FIELD
ADDR
R/W
BIT
00 = Control.
01 = Interrupt.
10 = Bulk.
11 = Isochronous.
0 = The transmit FIFO can hold only one packet.
1 = The transmit FIFO can hold more than one packet.
0 = No retransmission.
1 = Automatic frame retransmission is enabled. The frame is retransmitted if a transmit
an error occurred (time-out).
0
Note: The RTE bit can only be set if the transmit packet is contained in a single buffer.
1
EPN
R/W
(IMMR & 0xFFFF0000) + 0xA04 (USEP0), 0xA06 (USEP1), 0xA08 (USEP2), 0xA0A (USEP3)
0
Otherwise, retransmission must be handled by software intervention.
2
Freescale Semiconductor, Inc.
For More Information On This Product,
3
RESERVED
MPC823 REFERENCE MANUAL
4
R/W
0
Go to: www.freescale.com
5
6
R/W
TM
0
7
RESERVED
8
R/W
0
9
R/W
MF
10
0
RTE
R/W
11
0
12
THS
R/W
0
13
MOTOROLA
14
RHS
R/W
15