mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 424

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Memory Controller
15.6 EXTERNAL MASTER SUPPORT
The memory controller supports internal and external bus masters. Accesses that originate
from the core, CPM, and LCD controller are considered internal and those initiated by an
external bus master are external. External bus master support can be enabled in the SIU
module configuration register (SIUMCR), as indicated in Section 12.12.1.1 SIU Module
Configuration Register. There are two types of external bus masters:
Synchronous masters initiate a transfer by asserting the TS signal. The A[6:31], RD/WR,
and TSIZx signals must be stable prior to the rising edge of CLKOUT after TS assertion and
until the last TA signal is negated. Since the external master operates synchronously with
the MPC823, proper setup and hold times for all inputs associated with the rising edge of
CLKOUT are significant. To support synchronous mode using the memory controller, the
SEME bit in the SIUMCR must be set. When the TS signal is asserted, the memory
controller compares the address with each one of its defined valid banks and if a match is
found, control signals to the slave device are generated and the TA signal is supplied to the
external master. If the SEME bit is cleared, the memory controller is bypassed and the
external synchronous master must provide control signals to the slave device. See
Figure 15-35 for details.
Asynchronous masters initiate a transfer by driving the address bus and asserting the AS
pin. The A[6:31] signals, together with RD/WR and TSIZx, must have a proper setup time
prior to AS pin assertion. To support asynchronous mode using the memory controller, the
AEME bit in the SIUMCR must be set. The memory controller synchronizes AS assertion to
its internal clock and generates the control signals to the slave device. When the AS pin is
synchronized, the memory controller compares the address with each one of its defined
valid banks and if a match is found, control signals to the slave device are generated and
the TA signal is supplied to the external master. All the control signals to the memory device
and the TA signal are negated with AS pin negation. If the AEME bit is cleared, the memory
controller is bypassed and the external asynchronous master must provide control signals
to the slave device. In this mode, the AS pin of the MPC823 is not available as an input. See
Figure 15-36 for details.
• Synchronous bus masters, which synchronize with CLKOUT and may use the MPC823
• Asynchronous bus masters, which use an address strobe (AS) signal that handshakes
memory controller to access a slave device or bypass the memory controller to perform
the slave access.
with the MPC823 memory controller to access a slave device or bypass the memory
controller to perform the slave access.
Note: When external masters access slaves on the bus, the internal AT[0:2] signals
reaching the memory controller will be forced to ‘100’. You must make sure this
access matches the AT field in the base register after it is masked by the ATM
field in the option register.
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
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