mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 641

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Reception delays are determined by the CDx pin as illustrated in Figure 16-67. If the CDS
bit in the GSMR_H is zero, then the CDx pin is sampled on the rising receive clock edge
prior to data being received. If the CDS bit in the GSMR_H is 1, then the CDx pin transitions
cause data to be immediately gated into the receiver.
If the CDx pin is programmed to envelope the data, it must remain asserted during frame
transmission or a CDx lost error occurs. Negation of the CDx pin terminates reception. If the
CDS bit in the GSMR_H is zero, the CDx pin must be sampled by a serial communication
controller before a CDx lost error is recognized. Otherwise, the negation of CDx immediately
causes the CDx lost condition to occur.
(INPUT)
NOTES:
(INPUT)
NOTES:
(INPUT)
(INPUT)
RXDx
RCLK
1. CDS is set to 0 in the GSMR and CDP is set to 0.
RXDx
CDx
RCLK
1. CDS is set to 1 in the GSMR and CDP is set to 0.
CDx
2. If CDx is negated prior to the last bit of the receive frame, CDx lost is signaled in the frame buffer descriptor.
3. If CDP is set to 1, CDx lost cannot occur and CDx negation has no effect on reception.
2. If CDx is negated prior to the last bit of the receive frame, CDx lost is signaled in the frame buffer descriptor.
3. If CDP is set to 1, CDx lost cannot occur and CDx negation has no effect on reception.
Figure 16-67. Using CDx to Control Synchronous Protocol Reception
Note: If the CDS bit in the GSMR_H is set, all CDx transitions must occur while the
receive clock is low.
Freescale Semiconductor, Inc.
CDx ASSERTION IMMEDIATELY
GATES RECEPTION
FIRST BIT OF DATA IN FRAME
For More Information On This Product,
FIRST BIT OF FRAME DATA
CDx SAMPLED LOW HERE
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
CDx NEGATION IMMEDIATELY
LAST BIT OF FRAME DATA
CDx SAMPLED HIGH HERE
LAST BIT OF FRAME DATA
HALTS RECEPTION
Communication Processor Module
16-189