mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1038

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Video Controller
19.3.5 Video Frame Configuration Register (Set 0)
The 32-bit, memory mapped, read/write video frame configuration register set 0 (VFCR0)
holds the display horizontal and vertical size, as well as the gap between two sequential
lines.
SFB0—Single Frame Buffer 0
This bit controls whether the video controller displays an image from a single frame buffer
(A) or from both frame buffers (A and B).
Bits 1–2—Reserved
These bits are reserved and must be set to 0.
VPC0—Vertical Pixel Count 0
This field defines the number of lines for a field.
GAP0—Gap 0
This field defines the gap in memory between the end of a line and the beginning of the next
line in full burst units. For regular noninterlace mode, this field is set to 0. For regular
interlace mode, it is set to the value in the NBPL0 field. For example, hardware pan/scroll
options in a zoomed buffer can be implemented by using the GAP0 field with an appropriate
field buffer start address. For example, with 720 pixels in YC
VFCR0
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = Frame B is valid.
1 = Frame B is not valid.
SFB0 RESERVED
R/W
16
0
0
Note: The value of the VPC0 field must be non-zero or an error will occur.
17
1
R/W
0
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
GAP0
R/W
0
20
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
21
5
(IMMR & 0xFFFF0000) + 0x810
(IMMR & 0xFFFF0000) + 0x812
22
6
23
7
VPC0
R/W
0
24
8
25
9
10
26
format, GAP0 must be 0x5A.
11
27
NBPL0
R/W
0
12
28
13
29
MOTOROLA
GAP0
R/W
14
30
0
15
31