mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 207

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Data Cache
10.3.1.2 P
The data cache supports the following instructions:
10.3.1.3 P
data cache supports the dcbi (data cache block invalidate) instruction.
10.3.2 Implementation-Specific Operations
The MPC823 data cache includes some extended features in addition to those of the
PowerPC architecture. The following are implementation-specific operations supported by
the MPC823:
10.3.3 Special Registers of the Data Cache
The PowerPC special registers are accessed via the mtspr and mfspr instructions. The
following registers are used to control the data cache:
These registers are privileged and any attempt to access them while the core is in the
problem state (MSR
• Data cache block flush ( dcbf )
• Data cache block store ( dcbst )
• Data cache block touch (dcbt)
• Data cache block touch for store (dcbtst)
• Data cache block set to zero (dcbz)
• Block lock
• Block unlock
• Invalidate all
• Unlock all
• Flush cache line
• Read tags
• Read registers
• Data cache control and status register (DC_CST)
• Data cache address register (DC_ADR)
• Data cache data register (DC_DAT)
OWER
OWER
PC VIRTUAL ENVIRONMENT ARCHITECTURE (BOOK II)
PC OPERATING ENVIRONMENT ARCHITECTURE (BOOK III). The
PR
=1) results in a program interrupt.
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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