mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 561

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.6.3.12 IDMA STATUS REGISTERS. The 8-bit IDMA 1 and 2 status registers (IDSRx)
are used to report events recognized by the IDMA controller. When an event is recognized,
the IDMA controller sets the corresponding bit in the IDSRx. These memory-mapped
registers can be read at any time. A bit is reset by writing a one (writing a zero has no effect).
Bits 0–5 and 7—Reserved
These bits are reserved and must be set to 0.
DONE—IDMA Transfer Done
This bit indicates that the IDMA channel terminated a transfer. It will be set after the byte
count in the BCR of the single-buffer mode parameter RAM has reached zero.
IDSR1 AND IDSR2
RESET
• Field Base Address Register—This 32-bit register specifies the field destination base
• Number of Fields Per Frame Register—This 16-bit register specifies the number of field
• Lines Per Field Count Register —This 16-bit register specifies the number of lines per
• Lines Per Field Register—This 16-bit register specifies the number of remaining lines
• Bytes Per Line Register—This 16-bit register specifies the number of bytes per line. The
• Raw Bytes Register—This 16-bit register specifies the number of bytes to skip from the
FIELD
ADDR
R/W
BIT
address. FBAR is incremented by the number of bytes per line after each field. It is used
in interlaced mode only.
per frame. It is used in interlaced mode only. NFLD is decremented after each field.
field. It is used in interlaced mode only.
to the end of the field. It is used in interlaced mode only, and must be initialized to the
value of the LCR. L_CNT is decremented after each line.
value must be divisible by 16 for one burst per request, by 32 for two bursts per request,
or by 64 for four bursts per request. It is used in interlaced mode only.
end of one line to the beginning of the next line. It is used in interlaced mode only.
00 = One burst per request.
01 = Two burst per request.
10 = Reserved.
11 = Four bursts per request.
BPR—Bursts Per Request
This field determines how many bursts will be transferred per request.
0
Freescale Semiconductor, Inc.
1
For More Information On This Product,
(IMMR & 0xFFFF0000) + 0x910 (IDSR1), 0x918 (IDSR2)
MPC823 REFERENCE MANUAL
2
Go to: www.freescale.com
RESERVED
R/W
0
3
4
Communication Processor Module
5
DONE
R/W
6
0
RESERVED
R/W
16-109
7
0