mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 102

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

5.2 REGISTER MODEL
5.2.1 System Clock and Reset Control Register
The SPLL has a 32-bit control register that is powered by keep-alive power. The system
clock and reset control register (SCCR) is memory-mapped into the MPC823 system
interface unit’s register map.
Bits 0 and 3–5—Reserved
These bits are reserved and must be set to 0.
COM—Clock Output Module
This field controls the output buffer strength of the CLKOUT pin. When both bits are set, the
CLKOUT pin is held in the high state. These bits can be dynamically changed without
generating spikes on the CLKOUT pin. If the CLKOUT pin is not connected to external
circuits, both bits are must be set to minimize noise and power dissipation. The COM field
is cleared by hard reset.
SCCR
NOTE:
HRESET
HRESET
FIELD
ADDR
FIELD
ADDR
POR
POR
R/W
R/W
BIT
BIT
00 = Clock output enabled full-strength buffer.
01 = Clock output enabled half-strength output buffer.
10 = Reserved.
11 = Clock output disabled.
—
* RTDIV depends on the combination of MODCK1and MODCK2. RTSEL depends on MODCK1.
See Table 5-2 for more information.
† This field is set according to the default of the hard reset configuration word.
HRESET is hard reset and POR is power-on reset.
= undefined and # = unaffected.
RES
R/W
RES
R/W
16
—
0
0
0
0
17
1
DFSYNC
COM
R/W
R/W
#
0
0
0
18
2
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
DFBRG
R/W
RESERVED
0
0
R/W
20
MPC823 REFERENCE MANUAL
4
0
0
Go to: www.freescale.com
21
5
DFNL
TBS
R/W
R/W
22
6
#
0
0
0
(IMMR & 0xFFFF0000) + 0x280
(IMMR & 0xFFFF0000) + 0x282
RTDIV
R/W
23
7
*
#
RTSEL CRQEN PRQEN
R/W
24
8
*
#
DFNH
R/W
R/W
25
9
0
0
0
0
R/W
10
26
0
0
11
27
Clocks and Power Control
RESERVED
R/W
0
0
DFLCD
R/W
12
28
0
0
13
29
EBDF
R/W
†
†
14
30
DFALCD
R/W
0
0
RES
R/W
15
31
0
0
5-3