mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1077

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Development Capabilities and Interface
20.4.1 Trap Enable Mode
The trap enable mode allows the following incidents to transfer control into the core internal
development support logic.
In debug mode, the development port also controls the debug mode features of the core.
For more details, refer to Section 20.4.3 The Development Interface Port.
20.4.2 Debug Mode
Debug mode provides the development system with the following functions:
• An instruction trap enable signal is used to program the instruction breakpoint
• A load/store trap enable signal is used to program the load/store breakpoint on-the-fly.
• A nonmaskable breakpoint is used to assert the nonmaskable external breakpoint.
• A maskable breakpoint is used to assert the maskable external breakpoint.
• A VSYNC control code is used to assert and negate VSYNC operation.
• Controls and maintains all circumstances of processor execution.
• The development port can force the core to enter debug mode even when the external
• Debug mode can be entered immediately out of reset, thus allowing you to debug a
• The events that cause the machine to enter into debug mode can be selectively defined
• Contains a cause register that indicates why debug mode is entered.
• After entering debug mode, program execution continues where it first entered debug
• All instructions are fetched from the development port, while load/store accesses are
• A simple method is provided for memory dump and load via the data register of the
• The processor enters the privileged state (MSR
• An OR signal of all interrupt cause register bits enables the development port to detect
on-the-fly.
interrupts are disabled.
system without ROM.
through an enable register.
mode.
performed on the real system memory in debug mode.
development port that is accessed with mtspr and mfspr.
execution of any instruction and access to any storage location.
pending events while in debug mode. For example, the development port can detect a
debug mode access to nonexisting memory space.
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=0) in debug mode, thus allowing
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