mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 292

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
12.8.1 Periodic Interrupt Status and Control Register
The read/write periodic interrupt status and control register (PISCR) contains the interrupt
request level and the interrupt status bits. It also controls the 16 bits to be loaded in a
modulus counter.
PIRQ—Periodic Interrupt Request Level
This field allows you to configure any interrupt level for periodic interrupts. See Figure 12-2
for interrupt request levels.
PS—Periodic Interrupt Status
This bit can be negated by writing a 1 to it (zero has no effect).
Bits 9–12—Reserved
These bits are reserved and must be set to 0.
PIE—Periodic Interrupt Enable
PITF—Periodic Interrupt Timer Freeze Enable
PTE—Periodic Timer Enable
PISCR
RESET
FIELD
ADDR
R/W
BIT
0 = The periodic interrupt timer is unaffected.
1 = The periodic interrupt timer has issued an interrupt.
0 = Disables the PS bit.
1 = Enables the PS bit to generate an interrupt.
0 = The periodic interrupt timer is unaffected by the FRZ signal.
1 = The FRZ signal stops the periodic interrupt timer.
0 = The periodic interrupt timer is disabled.
1 = The periodic interrupt timer is enabled.
0
1
2
Freescale Semiconductor, Inc.
For More Information On This Product,
3
PIRQ
R/W
0
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
5
(IMMR & 0xFFFF0000) + 0x240
6
7
R/W
PS
8
0
9
RESERVED
10
R/W
0
11
System Interface Unit
12
R/W
PIE
13
0
PITF PTE
R/W
14
0
12-23
R/W
15
1

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