mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 796

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Communication Processor Module
TXB—TX Buffer
This bit indicates that a buffer has been transmitted on the Ethernet channel.
RXB—RX Buffer
This bit indicates that a buffer that was not a complete frame was received on the Ethernet
channel.
ETHERNET SCCE
HDLC SCCE
NOTES:
LEGEND:
TENA
CLSN
EVENTS
NOTES:
RENA
TXD
RXD
1. RXB event assumes receive buffers are 64 bytes each.
2. The RENA events, if required, must be programmed in the port C parallel I/O, not in the SCC itself.
3. The RXF interrupt may occur later than RENA due to receive FIFO latency.
1. TXB events assume the frame required two transmit buffers.
2. The GRA event assumes a GRACEFUL STOP TRANSMIT command was issued during frame transmission.
3. The TENA or CLSN events, if required, must be programmed in the port C parallel I/O, not in the SCC itself.
EVENTS
TRANSMITTED BY ETHERNET
D = Data, and CR = CRC bytes.
RECEIVED IN ETHERNET
P = Preamble, SFD = Start Frame Delimiter, DA and SA = Source/Destination Address, T/L = Type/Length,
TIME
FRAME
FRAME
LINE IDLE
LINE IDLE
Figure 16-108. Ethernet Interrupt Events Example
Freescale Semiconductor, Inc.
For More Information On This Product,
P
SFD
P
MPC823 REFERENCE MANUAL
SFD DA SA T/L
DA SA T/L
Go to: www.freescale.com
STORED IN RX BUFFER
TXB
TX BUFFER
STORED IN
D
RXB
D
CR
CR
RXF
TXB
GRA
LINE IDLE
LINE IDLE
MOTOROLA

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