mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 334

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

External Bus Interface
Figure 13-20 illustrates the basic protocol for bus arbitration. For more information, see
Section 12.12.1.1 SIU Module Configuration Register.
13.4.6.1 BUS REQUEST SIGNAL. The potential bus master asserts the BR signal to
request bus mastership. BR must be negated once the bus is granted, the bus is not busy,
and the new master can drive the bus. If more requests are pending, the master can keep
asserting its bus request as long as needed. When configured for external central
arbitration, the MPC823 drives this signal when it needs bus mastership. When the internal
on-chip arbiter is used, this signal is an input to the internal arbiter and must be driven by
the external bus master.
2. ASSERT BB TO BECOME NEXT
1. ASSERT BR
1. WAIT FOR BB TO BE
3. NEGATE BR
1. PREFORM DATA TRANSFER
1. NEGATE BB
ACKNOWLEDGE BUS MASTERSHIP
RELEASE BUS MASTERSHIP
OPERATE AS BUS MASTER
MASTER
REQUESTING DEVICE
REQUEST THE BUS
Freescale Semiconductor, Inc.
Figure 13-20. Bus Arbitration Flowchart
For More Information On This Product,
MPC823 REFERENCE MANUAL
NEGATED
Go to: www.freescale.com
1. NEGATE BG (MAY CHOOSE TO
1. ASSERT BG
KEEP IT ASSERTED TO PARK
BUS MASTER)
GRANT BUS ARBITRATION
TERMINATE ARBITRATION
ARBITER
MOTOROLA