mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 64

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

External Signals
SIGNAL
CS[0:5]
CE1_B
IRQ5
IRQ6
IRQ6
IRQ0
IRQ1
IRQ7
DP2
DP3
FRZ
CS6
BR
BG
BB
PIN NUMBER
See Table 2-2
breakout.
for pin
B11
C10
A11
A10
C14
D3
C2
N1
N2
N3
Table 2-1. Signal Descriptions (Continued)
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Data Parity 2—This bidirectional three-state signal provides parity generation and
checking for the data bus lane D[16:23] by transferring to a slave device initiated by
the MPC823. The parity function can be defined independently for each one of the
addressed memory banks (if controlled by the memory controller) and for the rest of
the slaves on the external bus.
Interrupt Request 5—This input signal is one of the eight external signals that can
request (by means of the internal interrupt controller) a service routine from the core.
Data Parity 3—This bidirectional three-state signal provides parity generation and
checking for the data bus lane D[24:31] by transferring to a slave device initiated by
the MPC823. The parity function can be defined independently for each one of the
addressed memory banks (if controlled by the memory controller) and for the rest of
the slaves on the external bus.
Interrupt Request 6 —This input signal is one of the eight external signals that can
request (by means of the internal interrupt controller) a service routine from the core.
It should be noted that the interrupt request signal that is sent to the interrupt
controller is the logical AND of this signal (if defined to function as IRQ6) and the
FRZ/IRQ6 if defined to function as IRQ6.
Bus Request—This bidirectional signal is asserted low when a possible master is
requesting ownership of the bus. When the MPC823 is configured to operate with the
internal arbiter, this signal is configured as an input. However, when the MPC823 is
configured to operate with an external arbiter, this signal is configured as an output
and asserted every time a new transaction is intended to be initiated and no parking
on the bus is granted.
Bus Grant —This bidirectional signal is asserted low when the arbiter of the external
bus grants the specific master ownership of the bus. When the MPC823 is
configured to operate with the internal arbiter, this signal is configured as an output
and asserted every time the external master asserts the BR signal and its priority
request is higher than any of the internal sources requiring the initiation of a bus
transfer. However, when the MPC823 is configured to operate with an external
arbiter, this signal is configured as an input.
Bus Busy —This bidirectional signal is asserted low by a master to show that it owns
the bus. The MPC823 asserts this signal after the bus arbiter grants it bus ownership
and the BB signal is negated.
Interrupt Request 6 —This input signal is one of the eight external signals that can
request (by means of the internal interrupt controller) a service routine from the core.
It should be noted that the interrupt request signal that is sent to the interrupt
controller is the logical AND of this signal (if defined to function as IRQ6) and the
DP3/IRQ6 (if defined to function as IRQ6.)
Freeze—This output signal is asserted to indicate that the internal core is in debug
mode.
Interrupt Request 0—This input signal is one of the eight external signals that can
request (by means of the internal interrupt controller) a service routine from the core.
It causes a non-maskable interrupt to the core.
Interrupt Request 1—This input signal is one of the eight external signals that can
request (by means of the internal interrupt controller) a service routine from the core.
Interrupt Request 7 —This input signal is one of the eight external signals that can
request (by means of the internal interrupt controller) a service routine from the core.
Chip Select —These output signals enable peripheral or memory devices at
programmed addresses if they are appropriately defined in the memory controller.
CS0 can be configured to be the global chip-select for the boot device.
Chip Select 6 —This output signal enables a peripheral or memory device at a
programmed address if defined appropriately in the BR6 and OR6 of the memory
controller.
Card Enable 1 Slot B —This output signal enables even byte transfers when
accesses to the PCMCIA Slot B are handled by the PCMCIA interface.
MPC823 REFERENCE MANUAL
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DESCRIPTION
MOTOROLA