mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 776

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
NOTE:
• C_PRES—For 32-bit CRC-CCITT, C_PRES must be initialized with 0xFFFFFFFF.
• C_MASK—For 32-bit CRC-CCITT, C_MASK must be initialized with 0xDEBB20E3.
• CRCEC, ALEC, and DISFC—These 32-bit (modulo 2
• PADS—You must write the pattern of the pad characters that must be sent when short
• RET_LIM—You must write the number of retries that must be made to transmit a frame
• RET_CNT is a temporary down-counter used to count the number of retries.
SCCx Base + 8C
SCCx Base + 9A
SCCx Base + 9C
SCCx Base + 9E
SCCx Base + A0
SCCx Base + A2
SCCx Base + 80
SCCx Base + 84
SCCx Base + 88
SCCx Base + 90
SCCx Base + 92
SCCx Base + 94
SCCx Base + 96
SCCx Base + 98
ADDRESS
communication processor module and you can initialize them while the channel is
disabled. CRCEC is incremented for each received frame with a CRC error, except it
does not include frames not addressed to you, frames received in the out-of-buffers
condition, frames with overrun errors, or frames with alignment errors. ALEC is
incremented for frames received with dribbling bits, but does not include frames not
addressed to you, frames received in the out-of-buffers condition, or frames with
overrun errors. DISFC is incremented for frames discarded because of the
out-of-buffers condition or an overrun error. The CRC does not have to be correct for
this counter to be incremented.
frame padding is implemented into this 16-bit register. The byte pattern written to the
register may be of any value, but both the high and low bytes must be the same.
into this 16-bit register. This value is typically 0xF. If the frame is not transmitted after
this limit is reached, an interrupt can be generated.
Table 16-30. SCCx Ethernet Parameter RAM Memory Map (Continued)
You are only responsible for initializing the items in bold. SCCx Base = (IMMR & 0xFFFF0000) + 0x3D00 (SCC2) and 0x3E00
(SCC3).
* The bytes inside each half-word are reversed.
All references to registers in the parameter RAM table are actually implemented in the dual-port RAM area as a memory-based
register.
TBUF1_DATA0
TBUF1_DATA1
TBUF1_RBA0
TBUF1_BCNT
TBUF1_CRC
BOFF_CNT
TADDR_M
TADDR_H
TADDR_L
TX_LEN
IADDR1
IADDR2
IADDR3
IADDR4
NAME
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Half-word
Half-word
Half-word
Half-word
Half-word
Half-word
Half-word
Half-word
Half-word
Half-word
WIDTH
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Word
Word
Word
Word
TX Frame Length Counter
Individual Address Filter 1
Individual Address Filter 2
Individual Address Filter 3
Individual Address Filter 4
Save Area 0–Next Frame
Save Area 1–Next Frame
Save BCNT–Next Frame
Save CRC–Next Frame
32
Save RBA–Next Frame
Temp Address (MSB)
Temp Address (LSB)
) counters are maintained by the
Backoff Counter
DESCRIPTION
Temp Address
MOTOROLA