mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 730

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
I—Interrupt
L—Last in Frame
This bit is set by the SCCx ASYNC HDLC controller when this buffer is the last in a frame.
If a closing flag or error is received, one or more of the BRK, CD, OV, and AB bits are set.
The SCCx ASYNC HDLC controller writes the number of frame octets to the DATA LENGTH
field.
F—First in Frame
This bit is set by the SCCx ASYNC HDLC controller when this buffer is the first in a frame.
CM—Continuous Mode
BRK—Break Character Received
This bit indicates that the current frame is closed when a break character is received.
BOF—Beginning of Frame Encountered
This bit indicates that the current frame is closed when a BOF character is received instead
of the expected EOF.
AB—RX Abort Sequence
This bit indicates that an asynchronous HDLC abort sequence or framing error is received
to terminate this frame.
CR—RX CRC Error
This bit indicates that this frame contains a CRC error. The received CRC bytes are always
written to the receive buffer.
OV—Overrun
This bit indicates that a receiver overrun has occurred during frame reception.
0 = The RXB bit in the SCCE–ASYNC HDLC register is not set after this buffer is used,
1 = The RXB or RXF bit in the SCCE–ASYNC HDLC register is set when this buffer is
0 = This buffer is not the last one in a frame.
1 = This buffer is the last one in a frame.
0 = The buffer is not the first one in a frame.
1 = The buffer is the first one in a frame.
0 = Normal operation.
1 = The E bit is not cleared by the communication processor module after this buffer
but RXF operation is unaffected.
used by the SCCx ASYNC HDLC controller.
descriptor is closed, thus allowing the associated data buffer to be automatically
overwritten next time the buffer descriptor is accessed by the communication
processor module. However, the E bit is cleared if an error other than CRC occurs
during reception, regardless of how the CM bit is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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