mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1060

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Development Capabilities and Interface
20.2.1.1.1 Special Case Queue Flush Information. There is one special case in which
the queue flush information is expected on the VF pins. This is easily monitored since this
can only happen when VF equals 111 and the maximum number of possible queue flushes
is five.
20.2.1.1.2 Program Trace In Debug Mode. When entering debug mode, an
interrupt/exception is reported on the VF pins (VF=100) and a cycle marked with the
program trace cycle is externally visible. When the CPU is in debug mode, the VF pins equal
000 and the VFLS pins equal 11. For more information on the MPC823 debug mode, refer
to Section 20.4 Hardware Development System Interface .
If the VSYNC signal is asserted/negated while the core is in debug mode, this information
is announced when the first VF pins report as the core returns to regular mode. If VSYNC
was not changed while in debug mode, the first VF pins report will be encoded as VF equals
101 (indirect branch) due to the rfi instruction being issued. In both cases, the first
instruction fetch after debug mode is marked with the program trace cycle attribute and is
externally visible. When the MPC823 external bus is configured to operate at half the speed
of the internal system (EBDF=1), the VF and VFLS pins will not report fetch and flush
information for the program trace capability. However, the internal freeze state of the
processor will be reported on the VFLS pins.
20.2.1.1.3 Sequential Instructions Marked As Indirect Branch. There are instances
where nonbranch or sequential instructions affect the machine similar to the way that
indirect branch instructions affect it. These sequential instructions include rfi , mtmsr , isync ,
and mtspr to the BAR, CMPA-CMPH, COUNTA, COUNTB, ICTRL, ICR, LCTRL1, LCTRL2,
and DER registers.
The core marks these instructions as indirect branch instructions (VF = 101) and the
following instruction address is marked with the program trace cycle attribute as if it was an
indirect branch target. Therefore, when one of these special instructions is detected in the
core, the address of the following instruction is externally visible. The reconstructing
software is now able to correctly evaluate the effect of these instructions.
20.2.1.2 THE EXTERNAL HARDWARE. When a program trace is needed, the external
hardware must sample the status pins—VF and VFLS—of every clock and mark the address
of all cycles with the program trace cycle attribute. Program trace is used in various ways,
but back trace and window trace are the most common methods.
MPC823 REFERENCE MANUAL
20-5
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