mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 233

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Memory Management Unit
11.6.1 Control Registers
11.6.1.1 MMU INSTRUCTION CONTROL REGISTER. The MMU instruction control
register (MI_CTR) is a special register that is used to control the operation of the instruction
memory management unit.
GPM—Group Protection Mode
PPM—Page Protection Mode
CIDEF—CI Default
Default value for instruction cache-inhibit attribute when the instruction MMU is disabled
(MSR
Bits 3 and 5—Reserved
These bits are reserved and must be set to 0. Ignored on write and returns a 0 on read.
RSV2I—Reserve Two Instruction TLB Entries
PPCS—Privilege/Problem State Compare Mode
Bits 7–20—Reserved
These bits are reserved and must be set to 0. Ignored on write and returns a 0 on read.
MI_CTR
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = PowerPC mode.
1 = Domain manager mode.
0 = Page resolution protection.
1 = 1K resolution protection for a 4K page.
0 = ITLB_INDX decremented modulo 8.
1 = ITLB_INDX decremented modulo 6.
0 = Ignore problem/privilege state during address compare.
1 = Consider problem/privilege state according to MI_RPN[24:27].
IR
= 0).
GPM
R/W
16
0
0
PPM
R/W
17
1
0
RESERVED
CIDEF
R/W
R/W
18
2
0
0
Freescale Semiconductor, Inc.
For More Information On This Product,
RES
R/W
19
3
0
RSV2I
R/W
20
MPC823 REFERENCE MANUAL
4
0
Go to: www.freescale.com
RES
R/W
21
5
0
ITLB_INDX
PPCS
R/W
R/W
22
6
0
0
23
7
SPR 784
SPR 784
24
8
25
9
10
26
RESERVED
R/W
11
27
RESERVED
0
R/W
0
12
28
13
29
MOTOROLA
14
30
15
31