mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1149

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

no operation (NOP)
scoreboard
sequential instruction
slave
snoop
swap
tablewalk
transaction
time-division multiplex (TDM)
watchpoint
word
writethrough
An instruction whose sole function is to increment the program counter, but which
A register tracking system that ensures that values are not pulled from a register before
Any instruction that is not a flow control instruction and not ISYNC.
A device that responds to the master’s address. A slave receives data on a write cycle
The act of monitoring external bus activity by alternate bus masters. By snooping these
Four byte lanes, reversing (lane 0 to lane 3, lane 1 to lane 2, lane 2 to lane 1 and lane
An index value is used to identify an entry point in a tree structure that is traversed until
A bus transaction consists of an address transfer (address phase) and data transfers
Any serial channel that is divided into channels separated by time.
An event that is reported, but does not change the timing of the machine.
A word consists of 4 bytes or 32 bits.
Continuous updates, as they occur, of external memory so that cache and memory
affects no changes to any registers or memory.
they are updated by a previous instruction.
and gives data to the master on a read cycle.
external accesses, a core can identify accesses to memory locations that contain dirty
data and possibly halt activity to supply correct data.
3 to lane 0).
a pointer is found. The system walks through a table of pointers to its end.
(data phase).
maintain coherency at all times.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Terminology
24-5