mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 705

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.9.16.15 SCC2 HDLC PROGRAMMING EXAMPLE #2.The following initialization
sequence is for an SCC2 HDLC channel that uses the DPLL in a Manchester encoding. You
must provide a clock that is 16 the preferred bit rate on the CLK3 pin. CLK3 is then
connected to the HDLC transmitter and receiver. A baud rate generator could also be used.
The SCC2 HDLC controller is configured with the RTS2, CTS2, and CD2 pins active.
21. Write 0x001A to the SCCM–HDLC to enable the TXE, RXF, and TXB interrupts.
22. Write 0x20000000 to the CIMR so the SCC2 can generate a system interrupt. The
23. Write 0x00000000 to the GSMR_H to enable normal behavior of the CTS2 and CD2
24. Write 0x00000000 to the GSMR_L to configure the CTS2 and CD2 pins to
25. Write 0x0000 to the PSMR–HDLC to configure one opening and one closing flag,
26. Write 0x00000030 to the GSMR_L to enable the SCC2 transmitter and receiver. This
1. Follow steps 1 through 22 in example #1 above.
2. Write 0x00000000 to the GSMR_H to enable normal behavior of the CTS2 and CD2
3. Write 0x004AA400 to the GSMR_L to configure the carrier sense as always active, a
4. Write 0x0000 to the PSMR–HDLC to configure one opening and one closing flag and
5. Write 0x004AA430 to the GSMR_L to enable the SCC2 transmitter and receiver. This
CICR must also be initialized.
pins and idles between frames (as opposed to flags).
automatically control transmission and reception and the HDLC mode. Normal
operation of the transmit clock is used. Notice that the transmitter (ENT) and receiver
(ENR) have not been enabled. If inverted HDLC operation is preferred, set the RINV
and TINV bits in the GSMR_L.
16-bit CCITT-CRC, and to prevent multiple frames in the FIFO.
additional write ensures that the ENT and ENR bits are enabled last.
pins and idles between frames.
16-bit preamble of “01” pattern, 16 operation of the DPLL for the receiver and
transmitter, Manchester encoding for the receiver and transmitter, and HDLC mode.
The CTS2 and CD2 pins must also be configured to automatically control transmission
and reception. Notice that the transmitter (ENT) and receiver (ENR) have not been
enabled yet.
16-bit CCITT-CRC. Multiple frames in the FIFO are not allowed in this example.
additional write ensures that the ENT and ENR bits are enabled last.
Note: After 5 bytes and CRC have been transmitted, the TX buffer descriptor is
automatically closed. Once a complete frame is received, the RX buffer
descriptor is closed. Any data received after 256 bytes or a single frame causes
a busy (out-of-buffers) condition since only one RX buffer descriptor is prepared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
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