mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 204

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

SECTION 10
DATA CACHE
The MPC823 data cache is a 1K two-way, set-associative cache. It is organized into 32 sets,
two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in
memory and can be used as an SRAM that allows the application to lock critical data
segments that need a fast and deterministic execution time. Two state bits are included in
each cache line and implement invalid, modified-valid, and unmodified-valid states of the
data cache. Cache coherency in a multiprocessor environment is maintained by the
software and supported by a fast hardware invalidation capability. The cache is designed for
both writeback and writethrough modes of operation and a least recently used (LRU)
replacement algorithm is used to select a line when no empty lines are available.
10.1 FEATURES
The following is a list of the data cache’s main features:
• 1K Two-Way, Set Associative, and Physically Addressed
• Single-Cycle Cache Access on Hit and 1 Clock Latency Added for Miss
• Four Word Line Size
• “Critical Word First” and Four Word Burst Line Fill
• Implements LRU Replacement Policy
• 32-Bit Interface to Load/Store Unit
• One-Word Write Buffer
• Lockable Cache Line Granularity
• Copyback/Writethrough Operation is Programmed per Memory Management Unit
• Coherency is Only Maintained by the Software and No Bus Snooping is Supported
• Cache Operation is Blocked under Miss, until the Critical Word is Delivered to the Core
• Hit Under Miss Operation
• Full Data Cache PowerPC
• Implementation-Specific Single Operation
Page
Freescale Semiconductor, Inc.
For More Information On This Product,
™
MPC823 REFERENCE MANUAL
Control Operations
Go to: www.freescale.com
10-1