mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 177

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

PowerPC Architecture Compliance
The following registers are set:
SRR0—Save/Restore Register 0
For I-breakpoints, set to the effective address of the instruction that caused the interrupt. For
L-breakpoint, set to the effective address of the instruction following the instruction that
caused the interrupt. For development port maskable request or a peripheral breakpoint, set
to the effective address of the instruction that the processor would have executed next if no
interrupt conditions were present. If the development port request is asserted at reset, the
value of SRR0 is undefined.
SRR1—Save/Restore Register 1
If the development port request is asserted at reset, the value of SRR1 is undefined.
MSR—Machine State Register
For L-bus breakpoint instances, the following registers are set to:
BAR—Breakpoint Address Register
Set to the effective address of the data access as computed by the instruction that caused
the interrupt.
DSISR—Data/Storage Interrupt Status Register
Do not change.
DAR—Data Address Register
Do not change.
The execution resumes from an address equal to the base indicated by the MSR
following offset.
• x’01D00’–For an instruction breakpoint match
• x’01C00’–For a data breakpoint match
• x’01E00’–For a development port maskable request or a peripheral breakpoint
• x’01F00’–For a development port nonmaskable request
1–4
10–15
Other
IP
ME
LE
Other
Set to 0.
Set to 0.
Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
No change.
No change.
Bits are copied from the ILE.
Set to 0.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
MOTOROLA
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