mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 688

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.9.16.6 SCCx HDLC COMMANDS.You can program the CPM command register
(CPCR) with the following commands to transmit data.
• STOP TRANSMIT—After the hardware or software is reset and the channel is enabled
• GRACEFUL STOP TRANSMIT—This command is used to stop transmission
• RESTART TRANSMIT—This command enables characters to be transmitted on the
• INIT TX PARAMETERS—This command initializes all transmit parameters in this serial
in the PSMR–SCC HDLC register, the channel is in transmit enable mode and starts
polling the first buffer descriptor in the table every 64 transmit clocks or immediately if
the TOD bit is set in the transmit-on-demand register (TODR). The channel STOP
TRANSMIT command disables the transmission of frames on the transmit channel. If
the SCCx HDLC controller receives this command while a frame is transmitting,
transmission is aborted after a maximum of 64 additional bits and the transmit FIFO is
flushed. The TBPTR is not advanced, no new buffer descriptor is accessed, and no new
frames are transmitted for this channel. The transmitter transmits an abort sequence
consisting of 01111111 (if the command was given during frame transmission) and
begins transmitting flags or idles, as indicated by the PSMR–SCC HDLC register.
smoothly, instead of abruptly, like the STOP TRANSMIT command. It stops
transmission after the current frame is finished or immediately if there is no frame being
transmitted. The GRA bit in the SCCE–HDLC is set once transmission has stopped.
Then the HDLC transmit parameters and their buffer descriptors can be modified. The
TBPTR points to the next TX buffer descriptor in the table. Transmission begins once
the R bit of the next buffer descriptor is set and the RESTART TRANSMIT command
is issued.
transmit channel. The SCCx HDLC controller expects this command after a STOP
TRANSMIT command is issued or after a GRACEFUL STOP TRANSMIT command is
issued or a transmitter error occurs. The SCCx HDLC controller resumes transmission
from the current TBPTR in the channel TX buffer descriptor table.
channel parameter RAM to their reset state and must only be issued when the
transmitter is disabled. The INIT TX AND RX PARAMS command can be used to reset
the transmit and receive parameters.
Note: If the MFF bit in the PSMR–SCC UART is set, one or more small frames can be
flushed from the transmit FIFO. Issue the GRACEFUL STOP TRANSMIT
command to prevent this from occurring.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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