mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 755

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.9.21.4.3 Transparent Synchronization Example. Figure 16-103 illustrates an
example of synchronization using the external signals.
MPC823 A and B in Figure 16-103 exchange transparent frames and synchronize each
other using the RTSx and CDx pins. However, the CTSx pin is not required since
transmission begins at any time. Thus, the RTSx pin is directly connected to the other
CCDxD pin. The RSYN bit in the GSMR_H is not set and transmission and reception from
each MPC823 is independent.
(OUTPUT
(OUTPUT
(OUTPUT
NOTES:
IS RXDx
IS CLKx
NOTES:
BRGOx
INPUT)
INPUT)
INPUT)
IS CDx
TXDx
1. CTSx should be configured as always asserted in the port C parallel I/O or externally connected to ground.
2. The required GSMR_x configurations are DIAG = 00, CTSS = 1, CTSP is a "don't care", CDS = 1, CDP = 0, TTX = 1, and
3. The transparent frame contains a CRC if the TC bit is set in the TX buffer descriptor.
RTSx
1. Each MPC82x generates its own transmit clocks. If the transmit and receive clocks are the same, one
TRX = 1. REVD and TCRC are application-dependent.
MPC82x can generate transmit and receive clocks for the other MPC82x. For example, CLKx on MPC82x (B) could be used to
clock the transmitter and receiver.
Figure 16-102. Sending Transparent Frames Between Each MPC823
MPC823 (A)
FIRST BIT OF FRAME DATA
BRGOx
Freescale Semiconductor, Inc.
RXDx
TXDx
RTSx
CLKx
CDx
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
CDx LOST CONDITION TERMINATES RECEPTION OF FRAME
L = 1 IN TX BD CAUSES NEGATION OF RTSx
LAST BIT OF FRAME DATA OR CRC
MPC823 (B)
RXDx
CDx
CLKx
RTSx
BRGOx
TXDx
Communication Processor Module
16-303