mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1110

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

20.6.3 Debug Mode Registers
20.6.3.1 INTERRUPT CAUSE REGISTER. The interrupt cause register (ICR) provides the
reason for entering debug mode. All bits are set by the hardware, cleared when the register
is read, and cleared to zero when exiting reset. Any attempt to write to this register is
ignored. The reset value for this register is 0x00000000.
ICR
Bits 0, 4, and 5—Reserved
These bits are reserved and must be set to 0.
RST—Reset Interrupt
This bit is set when the system reset pin is asserted. This pin is not implemented in the core.
CHSTP—Check Stop
This bit is set when the machine check interrupt is asserted and MSR
debug mode if enabled and the CHSTPE bit in the DER is set. Otherwise, the processor
enters the check stop state.
MCI—Machine Check Interrupt
This bit is set when the machine check interrupt is asserted and MSR
debug mode if enabled and the MCIE bit in the DER is set.
EXTI—External Interrupt
This bit is set when the external interrupt is asserted. The core enters debug mode if enabled
and the EXTIE bit in the DIR is set.
ALI—Alignment Interrupt
This bit is set when the alignment interrupt is asserted. The core enters debug mode if
enabled and the ALIE bit in the DIR is set.
RESET
RESET
FIELD
FIELD
R/W
SPR
R/W
SPR
BIT
BIT
RES
RES
16
0
R
R
0
0
RST
17
SEI
1
0
R
0
R
ITLBMS DTLBMS
CHSTP
18
2
0
R
0
R
Freescale Semiconductor, Inc.
For More Information On This Product,
MCI
19
3
0
R
0
R
ITLBER
MPC823 REFERENCE MANUAL
20
4
R
0
RESERVED
Go to: www.freescale.com
R
0
DTLBER
21
5
0
R
EXTI
22
6
R
0
23
ALI
7
R
0
148
148
PRI
24
RESERVED
8
R
0
Development Capabilities and Interface
R
0
FPUVI
25
9
0
R
DECI
10
26
R
0
11
27
RESERVED
ME
ME
R
0
=0. The core enters
=1. The core enters
LBRK
12
28
0
R
SYSI
IBRK
13
29
R
R
0
0
EBRK
14
30
TR
0
R
0
R
20-55
RES
15
31
DPI
R
R
0
0