mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 166

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

7.2.2 The Effect Of Operand Placement on Performance
The load/store unit hardware supports all of the PowerPC load/store instructions. An optimal
performance can be obtained for naturally aligned operands. These accesses result in
optimal performance for a maximum size of four bytes. Unaligned operands are supported
in the hardware and are broken into a series of aligned transfers. The effect of operand
placement on performance is as stated in the PowerPC Virtual Environment Architecture
(Book II), except for the case of 8-byte operands. Because the MPC823 uses a 32-bit wide
data bus, the performance is good rather than optimal . Refer to Section 6.6.6 Executing
Unaligned Instructions for a description of fixed-point unaligned instruction execution and
timing and to Section 6.6.9 Instruction Timing for a description of string instruction timing.
7.2.3 The Storage Control Instructions
The MPC823 interprets the cache control instructions ( icbi , isync , dcbt , dcbi , dcbf , dcbz ,
dcbst , eieio , and dcbtst ) as if they pertain only to the MPC823 cache. These instructions
do not broadcast. Any bus activity caused by these instructions is what happens when an
operation is performed on the MPC823 cache.
• Instruction Cache Block Invalidate ( icbi )—The effective address is translated by the
• Instruction Synchronize ( isync )—The isync instruction waits for all previous
• Data Cache Block Touch ( dcbt )—The block associated with this instruction is checked
• Data Cache Block Touch for Store ( dcbtst )—The block associated with this instruction
• Data Cache Block Set to Zero ( dcbz )—This instruction is executed according to how it
• Data Cache Block Store (dcbst)—This instruction is executed according to how it is
• Data Cache Block Invalidate (dcbi)—The effective address is translated by the memory
• Data Cache Block Flush (dcbf)—This instruction is executed according to how it is
• Enforce In-Order Execution of I/O (eieio)—When executing an eieio instruction, the
memory management unit and the associative block in the instruction cache is
invalidated if hit.
instructions to complete and then discards any prefetched instructions, thus causing
subsequent instructions to be fetched or refetched from memory and executed.
for hit in the cache. If it is a miss, the instruction is treated as a regular miss, except that
the bus error does not cause an interrupt. If no error occurs, the line is written into the
cache.
is checked for a hit in the cache. If it is a miss, the instruction is treated as a regular
miss, except that bus error does not cause an interrupt. If no error occurs, the cache
line is written into the cache.
is defined in the PowerPC Virtual Environment Architecture Book II .
defined in the PowerPC Virtual Environment Architecture Book II .
management unit and the associated block in the data cache is invalidated if hit.
defined in the PowerPC Virtual Environment Architecture Book II .
load/store unit waits until all previous accesses have terminated before issuing cycles
associated with load/store instructions after the eieio instruction.
Freescale Semiconductor, Inc.
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MPC823 REFERENCE MANUAL
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PowerPC Architecture Compliance
7-5