mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1315

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Index
branch prediction policy (table),
branch reservation station,
breakpoints,
breaks
BRG (definition),
BRGCLK divisor, defining,
BRGCLK,
BRGCx,
BRGO1,
BRGO2,
BRGO3,
BRGOUT2,
BS,
BS_B0,
BS_B1,
BS_B2,
BS_B3,
buffer chaining,
buffer descriptor ring
buffer descriptors
sending,
USB,
I2C controller
IDMA,
SCCx in ASYNC HDLC mode
SCCx in Ethernet mode
SCCx in HDLC mode
SCCx in Transparent mode
SCCx in UART mode
SCCx,
serial management controllers,
serial peripheral interface
SMC in Transparent mode
SMC in UART mode
universal serial bus
15-56
16-208
receive,
transmit,
receive,
transmit,
receive,
transmit,
receive,
transmit,
receive,
transmit,
receive,
transmit,
receive,
transmit,
receive,
transmit,
receive,
transmit,
receive,
2-5
2-5
2-5
2-5
16-157
2-8
2-9
2-9
16-372
5-19
16-96
16-175
2-9
,
20-9
16-209
2-9
16-91
16-466
16-277
16-337
16-241
16-307
16-217
16-444
16-415
16-396
16-363
16-154
16-468
16-279
16-340
16-245
16-309
16-221
16-446
16-417
16-400
15-27
6-6
Freescale Semiconductor, Inc.
For More Information On This Product,
6-6
16-381
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
burst access, initiated by the MPC823,
burst mechanism,
burst show cycle,
BURST,
bus arbitration and transfers,
bus bandwidth utilization, minimizing,
bus busy,
bus cycle access, requesting,
bus exceptions,
bus grant,
bus interface
bus interface,
bus master support,
bus master, becoming,
bus monitor,
bus request,
bus signals (illustration),
byte selects, enabling,
C
C/I (definition),
cache coherency,
cache hit,
cache inhibit,
cache miss,
CAM (definition),
cascaded mode,
CASID (definition),
CD2,
CD3,
CE1_B,
CE2_B,
channel reception
channel transmission
features,
operation
operation,
signal descriptions,
transfer signals,
SMC in GCI mode (C/I),
SMC in GCI mode (monitor),
SMC in GCI mode (C/I),
2-10
2-11
transmit,
address transfer phase signals,
arbitration phase signals,
basic transfers,
burst mechanism,
burst transfers,
data transfer phase signals,
exception control cycles,
single beat transfers,
storage reservation,
termination signals,
transfer alignment and packaging,
2-4
2-5
2-2
13-29
9-1
13-29
,
9-1
12-11
13-28
13-1
13-4
,
11-4
13-1
13-7
9-7
16-147
,
16-112
16-76
16-366
9-8
16-162
13-33
9-14
13-16
,
11-2
13-32
13-1
15-68
15-57
,
13-27
13-16
13-4
13-8
10-13
13-3
13-16
13-36
13-38
16-423
16-423
16-84
13-8
15-8
16-423
13-41
13-27
13-36
MOTOROLA
10-11
13-44
13-31
13-25