mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 258

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

11.6.2.3 MMU DATA RAM ENTRY READ REGISTER 1. The MMU data RAM entry read
register 1 (MD_RAM1) contains the protection mode information of the entry indexed by the
DTLB_INDX field of the MD_CTR. This register is only updated when you write a value to it.
Bits 0–16—Reserved
These bits are reserved and must be set to 0.
C—Change Bit for Data Entry TLB
EVF—Entry Valid Flag
MD_RAM1
NOTE: — = Undefined.
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = Unchanged region. Write access to this page results in the implementation-specific
1 = Changed region. Write access is allowed to this page.
0 = Entry is invalid.
1 = Entry is valid.
instruction MMU interrupt invocation. Software must take an appropriate action
before setting this bit to 1.
RES
16
0
0
R
17
—
1
C
R
EVF
18
—
2
R
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
20
MPC823 REFERENCE MANUAL
4
SA
—
R
Go to: www.freescale.com
21
5
22
6
SAT
23
—
7
RESERVED
R
SPR 826
SPR 826
R
0
URP0
24
—
8
R
UWP0
25
9
—
R
URP1
10
26
—
R
UWP1
11
27
—
Memory Management Unit
R
URP2
12
28
—
R
UWP2
13
29
—
R
URP3
14
30
—
R
11-41
UWP3
15
31
—
R