mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 399

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

15.5.1.3 SOFTWARE REQUESTS. The software can initiate a request to the
user-programmable machine by issuing one of three commands—read, write, or execute a
RAM word—to the memory command register. Every memory device has its own signal
handshaking protocol to put it into self-refresh mode or any special protocol mode. In the
user-programmable machine there are unused areas that enable you to write a special RAM
word for this protocol. Any unused area in the UPM RAM can be used to store these RAM
words. Typically, software requests are used to put the memory in self-refresh mode. You
can use this method to maintain memory integrity before entering low-power modes. A new
command must be issued to exit self-refresh mode or any special protocol mode after
returning to normal operation.
15.5.1.4 EXCEPTION REQUESTS. When an access to a memory device is initiated by the
MPC823 under UPM control, the external device may assert a TEA, SRESET, or HRESET
signal. The UPM provides a mechanism that allows you to handle the memory control
signals to meet the timing requirements of the device without losing data.
15.5.2 Programming the User-Programmable Machine
The user-programmable machine is a micro-sequencer that requires micro-instructions or
RAM words to generate signal timings for different memory cycles. You must program the
user-programmable machine in the following order:
Each user-programmable machine has a machine mode register (MxMR) that defines the
general attributes for operation. The PTA field of the MAMR and the PTB field of the MBMR
defines the period for the timers associated with UPMA and UPMB. If the PTAE bit is set,
the periodic timer of UPMA requests a transaction when the timer period expires. If the
PTBE bit is set, the periodic timer of UPMB requests a transaction when the timer period
expires.
To initiate a software request, issue the appropriate command to the memory command
register with the MAD field indexing the first entry of the UPM entry word. Command
execution is accomplished by accessing consecutive RAM words (one per clock) until the
word with the LAST bit set is encountered. The words read from the RAM provide
information about the value and timing of the external signals controlled by the UPM and
about specific strobes that control internal memory controller resources.
There is a disable timer mechanism associated with each user-programmable machine that
is only active between memory accesses. This timer is used to provide a delay between
successive memory cycles to the same bank.
1. Write a program into the RAM array.
2. Set up the base and option registers.
3. Program the memory periodic timer prescaler register.
4. Program the machine mode register.
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Memory Controller
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